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    Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information
    5.
    发明授权
    Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information 有权
    使用包括数据相关信息的增强型基本块向量来评估集成电路设计性能的方法和装置

    公开(公告)号：US07844928B2

    公开(公告)日：2010-11-30

    申请号：US11972747

    申请日：2008-01-11

    申请人： Robert H. Bell ,  Thomas W. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell ,  Thomas W. Chen ,  Richard J. Eickemeyer ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5022

    摘要： A test system or simulator includes an IC benchmark software program that executes application software on a semiconductor die IC design model. The benchmark software includes trace, simulation point, clustering and other programs. IC designers utilize the benchmark software to evaluate the performance characteristics of IC designs with customer user software applications. The benchmark software generates basic block vectors BBVs from instruction traces of application software. The benchmark software analyzes data dependent information that it appends to BBVs to create enhanced BBVs or EBBVs. The benchmark software may graph the EBBV information in a cluster diagram and selects a subset of EBBVs as a representative sample for each program phase. Benchmarking software generates a reduced application software program from the representative EBBV samples. Designers use the test system with benchmarking software to evaluate IC design model modifications by using the representative reduced application software program.

    摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行应用软件的IC基准软件程序。 基准软件包括跟踪，模拟点，聚类和其他程序。 IC设计人员利用基准软件来评估用户用户软件应用的IC设计的性能特征。 基准软件从应用软件的指令轨迹生成基本块向量BBV。 基准软件分析数据相关信息，它附加到BBV以创建增强型BBV或EBBV。 基准软件可以在一个聚类图中绘制EBBV信息，并选择一个EBBV子集作为每个程序阶段的代表性样本。 基准测试软件从代表性的EBBV样本中生成一个减少的应用软件程序。 设计人员使用带有基准测试软件的测试系统，通过使用代表性的减少应用软件程序来评估IC设计模型修改。

    Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information
    6.
    发明申请
    Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information 有权
    使用基本块向量和包含微体系结构信息的飞越向量评估集成电路设计模型性能的方法和装置

    公开(公告)号：US20090199138A1

    公开(公告)日：2009-08-06

    申请号：US12026141

    申请日：2008-02-05

    申请人： Robert H. Bell ,  Thomas W. Chen ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    发明人： Robert H. Bell ,  Thomas W. Chen ,  Venkat R. Indukuru ,  Pattabi M. Seshadri ,  Madhavi G. Valluri

    IPC分类号： G06F17/50

    CPC分类号： G06F11/3457 ,  G06F11/3428

    摘要： A test system or simulator includes an IC test application sampling software program that executes test application software on a semiconductor die IC design model. The test application sampling software includes trace, simulation point, CPI error, clustering and other programs. IC designers utilize the test application sampling software to evaluate the performance characteristics of IC designs with test software applications. The test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software. The test application sampling software analyzes microarchitecture dependent information that it uses to generate the FBVs. Test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing an instruction budgeting method. Designers use the test system with test application sampling software to evaluate IC design models by using the representative test application software program.

    摘要翻译： 测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的IC测试应用采样软件程序。 测试应用采样软件包括跟踪，仿真点，CPI错误，聚类等程序。 IC设计人员利用测试应用程序采样软件，通过测试软件应用来评估IC设计的性能特征。 测试应用采样软件从测试应用软件的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。 测试应用程序采样软件分析其用于生成FBV的微体系结构依赖信息。 测试应用采样软件使用指令预算方法从BBV和FBV数据生成降低的代表性测试应用软件程序。 设计人员使用带有测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

    METHOD AND CACHE SYSTEM WITH SOFT I-MRU MEMBER PROTECTION SCHEME DURING MAKE MRU ALLOCATION
    7.
    发明申请
    METHOD AND CACHE SYSTEM WITH SOFT I-MRU MEMBER PROTECTION SCHEME DURING MAKE MRU ALLOCATION 有权
    在制作MRU分配过程中使用软I-MRU成员保护方案的方法和缓存系统

    公开(公告)号：US20080082754A1

    公开(公告)日：2008-04-03

    申请号：US11538091

    申请日：2006-10-03

    申请人： Robert H. Bell ,  Jeffrey A. Stuecheli

    发明人： Robert H. Bell ,  Jeffrey A. Stuecheli

    IPC分类号： G06F13/00

    CPC分类号： G06F12/126

    摘要： A caching mechanism implementing a “soft” Instruction-Most Recently Used (I-MRU) protection scheme whereby the selected I-MRU member (cache line) is only protected for a limited number of eviction cycles unless that member is updated/utilized during the period. An update or access to the instruction restarts the countdown that determines when the cache line is no longer protected as the I-MRU. Accordingly, only frequently used Instruction lines are protected, and old I-MRU lines age out of the cache. The old I-MRU members are evicted, such that all the members of a congruence class may be used for data. The I-MRU aging is accomplished through a counter or a linear feedback shift register (LFSR)-based “shootdown” of I-MRU cache lines. The LFSR is tuned such that an I-MRU line will be protected for a pre-established number of evictions.

    摘要翻译： 实现“软”指令 - 最近使用（I-MRU）保护方案的缓存机制，由此所选择的I-MRU成员（高速缓存行）仅对有限数量的驱逐周期进行保护，除非该成员在 期。 对该指令的更新或访问将重新启动倒数计时，以确定高速缓存行何时不再受I-MRU的保护。 因此，只有经常使用的指令行被保护，并且旧的I-MRU线老化在高速缓存之外。 旧的I-MRU成员被驱逐出来，使得一致等级的所有成员都可以用于数据。 I-MRU老化通过I-MRU高速缓存线的计数器或线性反馈移位寄存器（LFSR）的“下降”来实现。 调整LFSR，使得I-MRU线路将受到预先确定的驱逐次数的保护。

    Buck regulators with adjustable clock frequency to achieve dropout voltage reduction
    8.
    发明授权
    Buck regulators with adjustable clock frequency to achieve dropout voltage reduction 有权
    降压稳压​​器可调节时钟频率，实现压降降压

    公开(公告)号：US08193798B1

    公开(公告)日：2012-06-05

    申请号：US12608676

    申请日：2009-10-29

    申请人： W. David Pace ,  Robert H. Bell ,  Steven L. Harris

    发明人： W. David Pace ,  Robert H. Bell ,  Steven L. Harris

    IPC分类号： G05F1/00

    CPC分类号： H02M3/156

    摘要： A method includes generating a drive signal for a transistor in a switching regulator. The drive signal turns the transistor on and off to generate a regulated output voltage. The drive signal is generated based on a clock signal. The method also includes dynamically decreasing a frequency of the clock signal to decrease a dropout voltage of the switching regulator. Dynamically decreasing the frequency of the clock signal can increase a duration of switching periods defined by the clock signal. The dropout voltage could have a first value proportional to TOFF—MIN/TON—MAX during shorter switching periods and a second value proportional to TOFF—MIN/TON—MAX—DFC during longer switching periods. TOFF—MIN represents a minimum amount of off-time for the transistor during each switching period, TON—MAX represents a maximum amount of on-time for the transistor during shorter switching periods, and TON—MAX—DFC represent a maximum amount of on-time for the transistor during longer switching periods.

    摘要翻译： 一种方法包括在开关调节器中产生晶体管的驱动信号。 驱动信号使晶体管导通和关断，以产生稳定的输出电压。 基于时钟信号产生驱动信号。 该方法还包括动态地降低时钟信号的频率以减小开关调节器的压差电压。 动态地降低时钟信号的频率可以增加由时钟信号限定的开关周期的持续时间。 在更短的开关周期期间，压差电压可以具有与TOFF-MIN / TON-MAX成比例的第一值，在较长的开关周期期间，与TOFF-MIN / TON-MAX-DFC成比例的第二值。 TOFF-MIN表示在每个开关周期期间晶体管的截止时间的最小值，TON-MAX表示在较短的开关周期期间晶体管的导通时间的最大值，TON-MAX-DFC表示最大的导通时间 在更长的开关周期内为晶体管提供时间。

    Ballistic resistant metal armor plate
    10.
    发明授权
    Ballistic resistant metal armor plate 失效
    防弹金属装甲板

    公开(公告)号：US5749140A

    公开(公告)日：1998-05-12

    申请号：US398934

    申请日：1995-03-06

    申请人： Anthony J. Polito ,  Ronald E. Bailey ,  William W. Timmons ,  Robert H. Bell

    发明人： Anthony J. Polito ,  Ronald E. Bailey ,  William W. Timmons ,  Robert H. Bell

    IPC分类号： C21D8/02 ,  C22C38/00 ,  C22C38/44 ,  C22C38/60 ,  F41H5/04

    CPC分类号： F41H5/045 ,  C22C38/60 ,  Y10T29/4998 ,  Y10T428/12965

    摘要： A method of producing steel armor plate having improved resistance to penetration by projectiles. The armor plate provides for intended inclusions, generally elliptically shaped, in the steel oriented substantially parallel to the plate surface. Those inclusions result from at least one element of the steel composition selected from the group of sulfur and oxygen. The steel armor plate may be useful with an increased inclusion level on the front approximately one-half portion of the dual hardness composite steel armor plate so as to spread out the force of the impact over a wider area.

    摘要翻译： 一种生产具有改进的弹丸穿透性的钢铠装板的方法。 铠装板在基本上平行于板表面定向的钢中提供通常为椭圆形的预期夹杂物。 这些夹杂物由选自硫和氧的组合中的至少一种元素组成。 钢铠装板可用于在双硬度复合钢铠装板的前面约一半部分上具有增加的夹杂物水平，以便在更宽的区域上展开冲击力。