公开(公告)号：US20090032904A1

公开(公告)日：2009-02-05

申请号：US11831208

申请日：2007-07-31

申请人： Anil K. Chinthakindi ,  Eric Thompson

发明人： Anil K. Chinthakindi ,  Eric Thompson

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized conductive fingers includes a first set of fingers that are connected to an anode terminal, and a second set of fingers that are connected to a cathode terminal. The plurality of layers includes a bottommost layer that is in closest proximity to a substrate relative to other layers of the plurality of layers. The bottommost layer does not include any fingers connected to the anode terminal.

摘要翻译： 多个交叉指状的导电指状物被布置成在由高介电常数材料分离的多个层中的每一层中形成基本上正方形的构造，其中多个交叉指状导电指状物中的每一个包括至少一个基本上90度的弯曲部。 多个交叉指状的导电指状物包括连接到阳极端子的第一组指状物和连接到阴极端子的第二组指状物。 多个层包括相对于多个层中的其它层最靠近衬底的最底层。 最底层不包括连接到阳极端子的任何手指。

公开(公告)号：US07551421B2

公开(公告)日：2009-06-23

申请号：US11616064

申请日：2006-12-26

申请人： Eric Thompson ,  Anil K. Chinthakindi

发明人： Eric Thompson ,  Anil K. Chinthakindi

IPC分类号： H01G4/228 ,  H01G4/005

CPC分类号： H01G4/306 ,  H01G4/232 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A capacitor is disclosed having reduced impedance. In one embodiment, the capacitor includes a cathode including a first terminal and a first set of electrodes extending from the first terminal in a first layer, each electrode in the first set coupled to one corresponding electrode of a second set of electrodes in a second layer by at least one contact; and an anode including a second terminal and a third set of electrodes extending from the second terminal in the second layer, each electrode in the third set coupled to one corresponding electrode of a fourth set of electrodes in the first layer by at least one contact, wherein the first terminal and the second terminal are on a same end of the capacitor.

摘要翻译： 公开了具有减小的阻抗的​​电容器。 在一个实施例中，电容器包括阴极，其包括第一端子和从第一层中的第一端子延伸的第一组电极，第一组中的每个电极耦合到第二层中的第二组电极的一个对应电极 至少有一个联系人; 以及包括从第二层中的第二端子延伸的第二端子和第三组电极的阳极，第三组中的每个电极通过至少一个触点耦合到第一层中的第四组电极的一个对应电极， 其中所述第一端子和所述第二端子位于所述电容器的同一端上。

公开(公告)号：US07456463B2

公开(公告)日：2008-11-25

申请号：US11671614

申请日：2007-02-06

申请人： Eric Thompson ,  Anil K. Chinthakindi

发明人： Eric Thompson ,  Anil K. Chinthakindi

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01G4/33 ,  H01G4/228 ,  H01G4/306 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capacitors are disclosed having reduced parasitic capacitance. In one embodiment, the capacitor includes a first set of electrodes, each electrode of the first set extending through at least one of a plurality of back-end-of-line (BEOL) layers above a substrate; a second set of electrodes, each electrode of the second set extending through at least one of the BEOL layers, and wherein each electrode of the second set extends to a greater depth of the plurality of BEOL layers than each electrode of the first set.

摘要翻译： 公开了具有降低的寄生电容的电容器。 在一个实施例中，电容器包括第一组电极，第一组的每个电极延伸穿过衬底上方的多个后端行（BEOL）层中的至少一个; 第二组电极，第二组的每个电极延伸穿过至少一个BEOL层，并且其中第二组的每个电极延伸到多个BEOL层的比第一组的每个电极更大的深度。

公开(公告)号：US20080151469A1

公开(公告)日：2008-06-26

申请号：US11616064

申请日：2006-12-26

申请人： Eric Thompson ,  Anil K. Chinthakindi

发明人： Eric Thompson ,  Anil K. Chinthakindi

IPC分类号： H01G4/005

CPC分类号： H01G4/306 ,  H01G4/232 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A capacitor is disclosed having reduced impedance. In one embodiment, the capacitor includes a cathode including a first terminal and a first set of electrodes extending from the first terminal in a first layer, each electrode in the first set coupled to one corresponding electrode of a second set of electrodes in a second layer by at least one contact; and an anode including a second terminal and a third set of electrodes extending from the second terminal in the second layer, each electrode in the third set coupled to one corresponding electrode of a fourth set of electrodes in the first layer by at least one contact, wherein the first terminal and the second terminal are on a same end of the capacitor.

摘要翻译： 公开了具有减小的阻抗的​​电容器。 在一个实施例中，电容器包括阴极，其包括第一端子和从第一层中的第一端子延伸的第一组电极，第一组中的每个电极耦合到第二层中的第二组电极的一个对应电极 至少有一个联系人; 以及包括从第二层中的第二端子延伸的第二端子和第三组电极的阳极，第三组中的每个电极通过至少一个触点耦合到第一层中的第四组电极的一个对应电极， 其中所述第一端子和所述第二端子位于所述电容器的同一端上。

公开(公告)号：US07701037B2

公开(公告)日：2010-04-20

申请号：US11831208

申请日：2007-07-31

申请人： Anil K. Chinthakindi ,  Eric Thompson

发明人： Anil K. Chinthakindi ,  Eric Thompson

IPC分类号： H01L29/00

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized conductive fingers includes a first set of fingers that are connected to an anode terminal, and a second set of fingers that are connected to a cathode terminal. The plurality of layers includes a bottommost layer that is in closest proximity to a substrate relative to other layers of the plurality of layers. The bottommost layer does not include any fingers connected to the anode terminal.

摘要翻译： 多个交叉指状的导电指状物被布置成在由高介电常数材料分离的多个层中的每一层中形成基本上正方形的构造，其中多个交叉指状导电指状物中的每一个包括至少一个基本上90度的弯曲部。 多个交叉指状的导电指状物包括连接到阳极端子的第一组指状物和连接到阴极端子的第二组指状物。 多个层包括相对于多个层中的其它层最靠近衬底的最底层。 最底层不包括连接到阳极端子的任何手指。

公开(公告)号：US20090039467A1

公开(公告)日：2009-02-12

申请号：US11834956

申请日：2007-08-07

申请人： Anil K. Chinthakindi ,  Eric Thompson

发明人： Anil K. Chinthakindi ,  Eric Thompson

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.

摘要翻译： 本公开提供具有与平面电容器集成的沟槽电容器的片上去耦电容器结构，以提供改进的总电容密度。 在一些实施例中，该结构包括至少一个深沟槽电容器，至少一个平面电容器和互连所述深沟槽和平面电容器的金属层。 在其他实施例中，该结构包括至少一个深沟槽电容器和与至少一个深沟槽电容器电连通的金属层。 所述至少一个深沟槽电容器在所述掺杂区域和所述内部电极之间具有浅沟槽隔离区域，掺杂区域，内部电极和电介质。 电介质具有终止在浅沟槽隔离区的下表面处的上边缘。

公开(公告)号：US07968929B2

公开(公告)日：2011-06-28

申请号：US11834961

申请日：2007-08-07

申请人： Anil K. Chinthakindi ,  Eric Thompson

发明人： Anil K. Chinthakindi ,  Eric Thompson

IPC分类号： H01L27/108 ,  H01L29/94

CPC分类号： H01L29/945 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.

摘要翻译： 本公开提供了片上去耦电容器结构，其具有与形成在后端线路布线中的无源电容集成的沟槽电容器，以提供改进的总电容密度。 在一些实施例中，该结构包括至少一个深沟槽电容器和形成在至少两个后端线路布线层中的无源电容器。 沟槽和无源电容器通过其中一个布线层进行电连接。 在其它实施例中，该结构包括至少一个深沟槽电容器，第一后端线路接线电平和第二后端线路布线电平。 具有电介质的深沟槽电容器，其具有终止于浅沟槽隔离区域的下表面处的上边缘。 第一布线电平与沟槽电容器电连通。 第二布线电平通过垂直连接器垂直电连接到第一布线层，以便形成无源电容器。

公开(公告)号：US07816762B2

公开(公告)日：2010-10-19

申请号：US11834956

申请日：2007-08-07

申请人： Anil K. Chinthakindi ,  Eric Thompson

发明人： Anil K. Chinthakindi ,  Eric Thompson

IPC分类号： H01L29/00

CPC分类号： H01L29/945 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with planar capacitors to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor, at least one planar capacitor, and a metal layer interconnecting said deep trench and planar capacitors. In other embodiments, the structure includes at least one deep trench capacitor and a metal layer in electrical communication with the at least one deep trench capacitor. The at least one deep trench capacitor has a shallow trench isolation region, a doped region, an inner electrode, and a dielectric between the doped region and the inner electrode. The dielectric has an upper edge that terminates at a lower surface of the shallow trench isolation region.

摘要翻译： 本公开提供具有与平面电容器集成的沟槽电容器的片上去耦电容器结构，以提供改进的总电容密度。 在一些实施例中，该结构包括至少一个深沟槽电容器，至少一个平面电容器和互连所述深沟槽和平面电容器的金属层。 在其他实施例中，该结构包括至少一个深沟槽电容器和与至少一个深沟槽电容器电连通的金属层。 所述至少一个深沟槽电容器在所述掺杂区域和所述内部电极之间具有浅沟槽隔离区域，掺杂区域，内部电极和电介质。 电介质具有终止在浅沟槽隔离区的下表面处的上边缘。

公开(公告)号：US20090039465A1

公开(公告)日：2009-02-12

申请号：US11834961

申请日：2007-08-07

申请人： Anil K. Chinthakindi ,  Eric Thompson

发明人： Anil K. Chinthakindi ,  Eric Thompson

IPC分类号： H01L29/92

CPC分类号： H01L29/945 ,  H01L23/5223 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.

摘要翻译： 本公开提供了片上去耦电容器结构，其具有与形成在后端线路布线中的无源电容集成的沟槽电容器，以提供改进的总电容密度。 在一些实施例中，该结构包括形成在至少两个后端线路布线层中的至少一个深沟槽电容器和无源电容器。 沟槽和无源电容器通过其中一个布线层进行电连接。 在其它实施例中，该结构包括至少一个深沟槽电容器，第一后端线路接线电平和第二后端线路布线电平。 具有电介质的深沟槽电容器，其具有终止于浅沟槽隔离区域的下表面处的上边缘。 第一布线电平与沟槽电容器电连通。 第二布线电平通过垂直连接器垂直电连接到第一布线层，以便形成无源电容器。

公开(公告)号：US20080186651A1

公开(公告)日：2008-08-07

申请号：US11671614

申请日：2007-02-06

申请人： Eric Thompson ,  Anil K. Chinthakindi

发明人： Eric Thompson ,  Anil K. Chinthakindi

IPC分类号： H01G4/228

CPC分类号： H01G4/33 ,  H01G4/228 ,  H01G4/306 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Capacitors are disclosed having reduced parasitic capacitance. In one embodiment, the capacitor includes a first set of electrodes, each electrode of the first set extending through at least one of a plurality of back-end-of-line (BEOL) layers above a substrate; a second set of electrodes, each electrode of the second set extending through at least one of the BEOL layers, and wherein each electrode of the second set extends to a greater depth of the plurality of BEOL layers than each electrode of the first set.

摘要翻译： 公开了具有降低的寄生电容的电容器。 在一个实施例中，电容器包括第一组电极，第一组的每个电极延伸穿过衬底上方的多个后端行（BEOL）层中的至少一个; 第二组电极，第二组的每个电极延伸穿过至少一个BEOL层，并且其中第二组的每个电极延伸到多个BEOL层的比第一组的每个电极更大的深度。