公开(公告)号：US20120166856A1

公开(公告)日：2012-06-28

申请号：US13172647

申请日：2011-06-29

申请人： Ankur BAL ,  Anupam JAIN

发明人： Ankur BAL ,  Anupam JAIN

IPC分类号： G06F1/12

CPC分类号： H03K5/135 ,  G06F1/12 ,  H04L7/0045 ,  H04L7/02

摘要： Signal synchronizing systems and methods are disclosed. A signal synchronizing system includes a sequential logic circuit to receive an input signal and to generate a plurality of intermediate signals from the input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal. A signal receiver includes a microcontroller and a signal synchronizer coupled to the microcontroller. The signal synchronizer includes a sequential logic circuit to receive an input signal from a transmitter and to generate a plurality of intermediate signals from the received input signal based on a clock signal. A logic circuit combines the intermediate signals to generate an output signal.

摘要翻译： 公开了信号同步系统和方法。 信号同步系统包括顺序逻辑电路，用于接收输入信号并根据时钟信号从输入信号产生多个中间信号。 逻辑电路组合中间信号以产生输出信号。 信号接收机包括耦合到微控制器的微控制器和信号同步器。 信号同步器包括顺序逻辑电路，用于接收来自发射机的输入信号，并且基于时钟信号从所接收的输入信号产生多个中间信号。 逻辑电路组合中间信号以产生输出信号。

公开(公告)号：US20130110898A1

公开(公告)日：2013-05-02

申请号：US13468924

申请日：2012-05-10

申请人： Ankur BAL ,  Anupam JAIN ,  Neha BHARGAVA

发明人： Ankur BAL ,  Anupam JAIN ,  Neha BHARGAVA

IPC分类号： G06F17/10

CPC分类号： H03H17/0664

摘要： A signal processor includes one or more memory banks, wherein each memory bank stores filter coefficients; and one or more coefficient multiplexer units; each coefficient multiplexer unit being associated with a memory bank, and retrieves a filter coefficient based on a number of received input samples. The processor includes one or more multiply and accumulate (MAC) units, each MAC unit being associated with a coefficient multiplexer unit and determines a product of the retrieved filter coefficient with an input sample; retrieves a previous value stored in an associated register; computes a summation of the previous value and the product; and stores the summation in the associated register. The processor includes an output multiplexer unit to select a register, and to provide a value stored in the register as an output.

摘要翻译： 信号处理器包括一个或多个存储体，其中每个存储体存储滤波器系数; 和一个或多个系数多路复用器单元; 每个系数多路复用器单元与存储器组相关联，并且基于所接收的输入采样的数量来检索滤波器系数。 处理器包括一个或多个乘法和累积（MAC）单元，每个MAC单元与系数多路复用器单元相关联，并且确定所检索的滤波器系数与输入采样的乘积; 检索存储在相关联寄存器中的先前值; 计算以前的值和乘积的总和; 并将求和存储在相关联的寄存器中。 处理器包括输出多路复用器单元，用于选择寄存器，并将存储在寄存器中的值提供为输出。

公开(公告)号：US20120176264A1

公开(公告)日：2012-07-12

申请号：US13422833

申请日：2012-03-16

申请人： Rakhel Kumar PARIDA ,  Ankur BAL ,  Anil KUMAR ,  Anupam JAIN

发明人： Rakhel Kumar PARIDA ,  Ankur BAL ,  Anil KUMAR ,  Anupam JAIN

IPC分类号： H03M1/66

CPC分类号： H03M7/12 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M7/14

摘要： A dynamic element matching (DEM) scheme is implemented in a crawling code generator for converting a b-bit binary input code into a (2b−1)-bit digital output code. A random generator determines for every conversion step a direction. A decimal difference between the current and previous binary input is calculated. The new crawling output code is determined based on the previous crawling output code, the direction and the decimal difference. The DEM scheme is used in a digital-to-analog converter such that the crawling output code switches digital-to-analog converting elements that output analog signals that are then summed to be the final analog signal.

摘要翻译： 用于将b位二进制输入代码转换为（2b-1）位数字输出代码的爬行码生成器中实现动态元素匹配（DEM）方案。 随机生成器确定每个转换步骤一个方向。 计算当前和前一个二进制输入之间的十进制差值。 新的爬行输出代码基于先前的爬行输出代码，方向和小数差来确定。 DEM方案用于数模转换器，使得爬行输出码切换输出模拟信号的数模转换元件，然后将模拟信号相加为最终的模拟信号。