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    Digital signal processing block having a wide multiplexer
    4.
    发明申请
    Digital signal processing block having a wide multiplexer 有权
    具有宽多路复用器的数字信号处理块

    公开(公告)号：US20060212499A1

    公开(公告)日：2006-09-21

    申请号：US11433120

    申请日：2006-05-12

    申请人： Bernard New ,  Vasisht Vadi ,  Jennifer Wong ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  James Simkins

    发明人： Bernard New ,  Vasisht Vadi ,  Jennifer Wong ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  James Simkins

    IPC分类号： G06F15/00

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： A digital signal processing block having: 1) a first digital signal processing element including: a first multiplexer of a first plurality of multiplexers, the first multiplexer selecting between a first data input and a first zero constant input; and a first arithmetic unit coupled to the first plurality of multiplexers, the first arithmetic logic unit configured for addition; and 2) a second digital signal processing element including: a second multiplexer of a second plurality of multiplexers, the second multiplexer selecting between a second data input and a second zero constant input; and a second arithmetic unit coupled to the second plurality of multiplexers and to a third multiplexer of the first plurality of multiplexers, the second arithmetic unit configured for addition.

    摘要翻译： 一种数字信号处理块，具有：1）第一数字信号处理元件，包括：第一多路复用器的第一多路复用器，所述第一多路复用器在第一数据输入和第一零常数输入之间进行选择; 以及耦合到所述第一多个复用器的第一算术单元，所述第一算术逻辑单元被配置为用于相加; 以及2）第二数字信号处理元件，包括：第二多路复用器的第二多路复用器，所述第二多路复用器在第二数据输入和第二零常数输入之间进行选择; 以及耦合到所述第二多路复用器的第二运算单元和所述第一多路复用器的第三多路复用器，所述第二运算单元被配置为相加。

    Digital signal processing circuit having input register blocks
    6.
    发明申请
    Digital signal processing circuit having input register blocks 有权
    具有输入寄存器块的数字信号处理电路

    公开(公告)号：US20060230094A1

    公开(公告)日：2006-10-12

    申请号：US11432823

    申请日：2006-05-12

    申请人： James Simkins ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  Vasisht Vadi

    发明人： James Simkins ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  Vasisht Vadi

    IPC分类号： G06F7/52

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： An integrated circuit that includes a digital signal processing element (DSPE) having a first and a second register block coupled to a first arithmetic logic unit (ALU) circuit; a middle DSPE adjacent to the top DSPE having a third and a fourth register block coupled to a second ALU circuit, where the third register block is coupled to the first register block, and the fourth register block register block is coupled to the second register block; and a bottom DSPE adjacent to the middle DSPE having a fifth and a sixth register block coupled to a third ALU circuit, where the fifth register block is coupled to the third register block and the sixth register block register block is coupled to the fourth register block.

    摘要翻译： 一种集成电路，包括具有耦合到第一算术逻辑单元（ALU）电路的第一和第二寄存器块的数字信号处理元件（DSPE）; 与顶部DSPE相邻的中间DSPE具有耦合到第二ALU电路的第三和第四寄存器块，其中第三寄存器块耦合到第一寄存器块，并且第四寄存器块寄存器块耦合到第二寄存器块 ; 以及与中间DSPE相邻的底部DSPE，具有耦合到第三ALU电路的第五和第六寄存器块，其中第五寄存器块耦合到第三寄存器块，并且第六寄存器块寄存器块耦合到第四寄存器块 。

    Digital signal processing circuit having a SIMD circuit
    8.
    发明申请
    Digital signal processing circuit having a SIMD circuit 有权
    具有SIMD电路的数字信号处理电路

    公开(公告)号：US20060288069A1

    公开(公告)日：2006-12-21

    申请号：US11433331

    申请日：2006-05-12

    申请人： James Simkins ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  Vasisht Vadi

    发明人： James Simkins ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  John Thendean ,  Anna Wong ,  Vasisht Vadi

    IPC分类号： G06F7/38

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： An Integrated Circuit (IC) having a single-instruction-multiple-data (SIMD) is disclosed. The SIMD circuit includes: a plurality of multiplexers controlled by a first opcode; and an arithmetic logic unit (ALU) coupled to the plurality of multiplexers and controlled by a second opcode; and wherein the ALU has a plurality of adders, where the plurality of adders are controlled by some bits of the second opcode, and where a first adder of the plurality of adders adds a plurality of input bits to produce first summation bits and a first carry bit; the first adder operating concurrently with the other adders of the plurality of adders.

    摘要翻译： 公开了具有单指令多数据（SIMD）的集成电路（IC）。 SIMD电路包括：由第一操作码控制的多个多路复用器; 以及耦合到所述多个多路复用器并由第二操作码控制的算术逻辑单元（ALU）; 并且其中所述ALU具有多个加法器，其中所述多个加法器由所述第二操作码的某些位控制，并且其中所述多个加法器中的第一加法器添加多个输入位以产生第一求和位和第一进位 位 所述第一加法器与所述多个加法器的其它加法器同时运行。

    Digital signal processing circuit having an adder circuit with carry-outs
    9.
    发明申请
    Digital signal processing circuit having an adder circuit with carry-outs 有权
    数字信号处理电路具有进位输出的加法电路

    公开(公告)号：US20060230096A1

    公开(公告)日：2006-10-12

    申请号：US11433517

    申请日：2006-05-12

    申请人： John Thendean ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  James Simkins ,  Anna Wong ,  Vasisht Vadi

    发明人： John Thendean ,  Jennifer Wong ,  Bernard New ,  Alvin Ching ,  James Simkins ,  Anna Wong ,  Vasisht Vadi

    IPC分类号： G06F7/50

    CPC分类号： G06F7/02 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/575 ,  G06F2207/025 ,  G06F2207/3828 ,  G06K9/00986 ,  H03K19/1737

    摘要： An integrated circuit having a digital signal processing (DSP) circuit is disclosed. The DSP circuit includes: a plurality of multiplexers receiving a first set, second set, and third set of input data bits, where the plurality of multiplexers are coupled to a first opcode register; a bitwise adder coupled to the plurality of multiplexers for generating a sum set of bits and a carry set of bits from bitwise adding together the first, second, and third set of input data bits; and a second adder coupled to the bitwise adder for adding together the sum set of bits and carry set of bits to produce a summation set of bits and a plurality of carry-out bits, where the second adder is coupled to a second opcode register.

    摘要翻译： 公开了一种具有数字信号处理（DSP）电路的集成电路。 DSP电路包括：多个多路复用器，其接收第一组，第二组和第三组输入数据位，其中多个复用器耦合到第一操作码寄存器; 耦合到所述多个多路复用器的按位加法器，用于从所述第一，第二和第三输入数据位组合中逐位地生成位组和位的进位组; 以及第二加法器，其耦合到所述按位加法器，用于将所述位的总和相加和进位位组，以产生位和和多个进位位的求和集合，其中所述第二加法器耦合到第二操作码寄存器。