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    Integrated circuit testing methods using well bias modification
    1.
    发明授权
    Integrated circuit testing methods using well bias modification 失效
    集成电路测试方法采用偏置修正

    公开(公告)号：US07400162B2

    公开(公告)日：2008-07-15

    申请号：US10539247

    申请日：2003-02-20

    申请人： Anne Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

    发明人： Anne Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

    摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

    摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

    Integrated circuit testing methods using well bias modification
    2.
    发明授权
    Integrated circuit testing methods using well bias modification 失效
    集成电路测试方法采用偏置修正

    公开(公告)号：US07564256B2

    公开(公告)日：2009-07-21

    申请号：US12119834

    申请日：2008-05-13

    申请人： Anne Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

    发明人： Anne Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/3008 ,  G01R31/31858

    摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

    摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

    Integrated circuit testing methods using well bias modification
    4.
    发明授权
    Integrated circuit testing methods using well bias modification 失效
    集成电路测试方法采用偏置修正

    公开(公告)号：US07759960B2

    公开(公告)日：2010-07-20

    申请号：US12103906

    申请日：2008-04-16

    申请人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

    发明人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

    摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

    摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

    INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION
    6.
    发明申请
    INTEGRATED CIRCUIT TESTING METHODS USING WELL BIAS MODIFICATION 失效
    集成电路测试方法使用良好的偏差修正

    公开(公告)号：US20080211530A1

    公开(公告)日：2008-09-04

    申请号：US12103906

    申请日：2008-04-16

    申请人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

    发明人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

    摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

    摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

    Methods and apparatus for margin testing integrated circuits using asynchronously timed varied supply voltage and test patterns
    7.
    发明授权
    Methods and apparatus for margin testing integrated circuits using asynchronously timed varied supply voltage and test patterns 有权
    使用异步定时变化的电源电压和测试模式的集成电路余量测试的方法和装置

    公开(公告)号：US08854073B2

    公开(公告)日：2014-10-07

    申请号：US13236696

    申请日：2011-09-20

    申请人： David A. Grosch ,  Marc D. Knox ,  Erik A. Nelson ,  Brian C. Noble

    发明人： David A. Grosch ,  Marc D. Knox ,  Erik A. Nelson ,  Brian C. Noble

    IPC分类号： G01R31/02 ,  G01R31/3187 ,  G01R31/30

    CPC分类号： G01R31/30 ,  G01R31/3004

    摘要： Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.

    摘要翻译： 集成电路边缘检验方法和装置。 该方法包括：选择时钟频率，工作温度范围和用于对集成电路进行裕度测试的电源电压电平，其中时钟频率，工作温度范围和电源电压电平中的一个或多个在正常操作条件之外 的集成电路; 对集成电路施加与所选择的电源电压电平设定的异步时变电源电压; 以选定的时钟频率运行集成电路芯片，并将集成电路保持在所选择的温度范围内; 对集成电路施加连续测试图案; 并监控集成电路是否发生故障。