公开(公告)号：US4521765A

公开(公告)日：1985-06-04

申请号：US491600

申请日：1983-05-04

申请人： Anthony D. Wang ,  Donald L. Brumbaugh

发明人： Anthony D. Wang ,  Donald L. Brumbaugh

IPC分类号： H03M1/78 ,  H03M1/00 ,  H03M1/06 ,  H03M1/68 ,  H03M1/74 ,  H03K13/02

CPC分类号： H03M1/0612 ,  H03M1/68 ,  H03M1/745 ,  H03M1/785

摘要： An integrated circuit digital to analog converter includes circuitry having first and second resistors in a R/2R resistor ladder which scales bit current contributions to an analog output current. Each of the first and second resistors have a respective terminal connected to the collector of a bit current transistor, the emitter of which is connected to the emitter of a waste current transistor. The digital to analog converter includes a metal ground voltage conductor having a "shared node" and a distributed resistance between one side of the shared node and a main ground voltage connection. The collector of the waste current transistor and a second terminal of the first resistor are both connected directly to the shared node. In operation, the waste current transistor switches waste current into the shared node, rather than into a separate waste current ground conductor. This results in substantially less voltage variation across the distributed resistance of the metal ground voltage conductor, and consequently lower non-linearity, than is the case if waste current is switched into the separate ground conductor.

摘要翻译： 集成电路数模转换器包括具有R / 2R电阻梯中的第一和第二电阻器的电路，其对比模拟输出电流的比特电流贡献。 第一和第二电阻器中的每一个具有连接到位电流晶体管的集电极的相应端子，其发射极连接到废电流晶体管的发射极。 数模转换器包括具有共享节点的金属接地电压导体和共享节点的一侧与主接地电压连接之间的分布电阻。 废电流晶体管的收集器和第一电阻器的第二端子都直接连接到共享节点。 在运行中，废电流晶体管将浪费电流切换到共享节点，而不是分成废电流接地导体。 这导致金属接地电压导体的分布电阻之间的电压变化实质上更小，因此与废电流切换到单独接地导体的情况相比，具有更低的非线性。

公开(公告)号：US4468652A

公开(公告)日：1984-08-28

申请号：US421506

申请日：1982-09-22

申请人： Anthony D. Wang ,  Donald L. Brumbaugh

发明人： Anthony D. Wang ,  Donald L. Brumbaugh

IPC分类号： H03M1/06 ,  H03M1/68 ,  H03M1/74 ,  H03M1/78 ,  H03K13/02

CPC分类号： H03M1/0612 ,  H03M1/68 ,  H03M1/745 ,  H03M1/785

摘要： A monolithic digital-to-analog converter integrated circuit is disclosed including a first plurality of more significant bit switches having scaled bit switch currents and including a second plurality of lesser significant bit switches, the output nodes of which are coupled to a ladder network which contributes a binary-weighted portion of each lesser significant bit switch current to the summed analog output current. First and second output conductors, separate and apart from one another, are used to couple the output nodes of the more significant bit switches and the output current of the ladder network, respectively, to the analog output current pad. First and second ground voltage pads are included for isolating waste current conducted by the more significant bit switches from currents returned by the ladder network to the ground voltage. The waste current nodes of the lesser significant bit switches are conducted to the same ground voltage pad that conducts the currents returned by the ladder network.

摘要翻译： 公开了一种单片数模转换器集成电路，其包括具有缩放比特开关电流的第一多个更高有效位开关，并且包括第二多个较低有效位开关，其输出节点耦合到梯形网络 每个较低有效位开关电流的二进制加权部分到求和的模拟输出电流。 第一和第二输出导体彼此分离和分开用于将更高有效位开关的输出节点和梯形网络的输出电流分别耦合到模拟输出电流焊盘。 包括第一和第二接地电压焊盘，用于将由梯形网络返回的电流传导到更高有效位开关的浪涌电流与接地电压隔离。 较低有效位开关的废电流节点传导到导通梯形网络返回的电流的同一接地电压焊盘。