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1.发明授权Maintaining snoop traffic throughput in presence of an atomic operation a first port for a first queue tracks cache requests and a second port for a second queue snoops that have yet to be filtered 有权在存在原子操作的情况下维持侦测流量吞吐量第一个队列的第一个端口跟踪高速缓存请求，而第二个端口用于尚未被过滤的第二个队列窥探公开(公告)号：US06389517B1
公开(公告)日：2002-05-14
申请号：US09513034
申请日：2000-02-25
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/126
摘要： Apparatus and method to permit snoop filtering to occur while an atomic operation is pending. The snoop filtering apparatus includes first and second request queues and a cache. The first request queue tracks cache access requests, while the second request queue tracks snoops that have yet to be filtered. The cache includes a dedicated port for each request queue. The first port is dedicated to the first request queue and is a data-and-tag read-write port, permitting modification of both a cache line's data and tag. In contrast, the second port is dedicated to the second request queue and is a tag-only port. Because the second port is a tag-only port, snoop filtering can continue while a cache line is locked without fear of any modification of the data associated with the atomic address.
摘要翻译： 在原子操作待定时允许进行窥探过滤的装置和方法。 侦听过滤装置包括第一和第二请求队列和高速缓存。 第一个请求队列跟踪缓存访问请求，而第二个请求队列跟踪尚未过滤的窥探。 缓存包括每个请求队列的专用端口。 第一个端口专用于第一个请求队列，是一个数据和标签读写端口，允许修改高速缓存线的数据和标签。 相比之下，第二个端口专用于第二个请求队列，是一个仅标签端口。 因为第二个端口是只有标签的端口，所以可以在高速缓存行被锁定的同时继续进行监听过滤，而不用担心与原子地址相关联的数据的任何修改。
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2.发明授权Apparatus and method for preventing cache data eviction during an atomic operation 有权用于在原子操作期间防止高速缓存数据驱逐的装置和方法公开(公告)号：US06347360B1
公开(公告)日：2002-02-12
申请号：US09513033
申请日：2000-02-25
IPC分类号： G06F1200
CPC分类号： G06F12/126 , G06F12/0831
摘要： Apparatus and method for protecting cache data from eviction during an atomic operation. The apparatus includes a first request queue, a second request queue, and an atomic address block. The first request queue stores an entry for each cache access request. Each entry includes a first set of address bits and an atomic bit. The first set of address bits represents a first cache address associated with the cache access request and the atomic bit indicates whether the cache access request is associated with the atomic operation. The second request queue stores an entry for each cache eviction request. Each entry of the second request queue includes a second set of address bits indicating a second cache address associated with the cache eviction request. The atomic address block prevents eviction of a third cache address during the atomic operation on the third cache address. During a first clock cycle the atomic address block receives and analyzes a first set of signals representing a first entry of the first request queue to determine whether they represent the atomic operation. If so, the atomic address block sets a third set of address bits to a value representative of the first cache address. During a second clock cycle during which the atomic operation is being executed the atomic address block receives and analyzes a second set of signals representing the second set of address bits to determine whether the second set of address bits represent a same cache address as the third set of address bits. If so, the atomic address block stalls servicing of the second request queue, thus preventing eviction of data from the cache upon which an atomic operation is being performed.
摘要翻译： 用于在原子操作期间保护缓存数据免于驱逐的装置和方法。 该装置包括第一请求队列，第二请求队列和原子地址块。 第一个请求队列存储每个缓存访问请求的条目。 每个条目包括第一组地址位和原子位。 第一组地址位表示与高速缓存访问请求相关联的第一高速缓存地址，并且原子位指示高速缓存访问请求是否与原子操作相关联。 第二个请求队列存储每个缓存逐出请求的条目。 第二请求队列的每个条目包括指示与缓存驱逐请求相关联的第二高速缓存地址的第二组地址位。 原子地址块防止在第三高速缓存地址的原子操作期间驱逐第三高速缓存地址。 在第一时钟周期期间，原子地址块接收并分析表示第一请求队列的第一条目的第一组信号，以确定它们是否表示原子操作。 如果是，则原子地址块将第三组地址位设置为表示第一高速缓存地址的值。 在原子操作正在执行的第二时钟周期期间，原子地址块接收并分析表示第二组地址位的第二组信号，以确定第二组地址位是否表示与第三组相同的高速缓存地址 的地址位。 如果是，则原子地址块停止对第二请求队列的服务，从而防止从正在执行原子操作的高速缓存的数据的驱逐。
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3.发明授权Apparatus and method to prevent overwriting of modified cache entries prior to write back 有权在回写前防止修改缓存条目覆盖的装置和方法公开(公告)号：US06286082B1
公开(公告)日：2001-09-04
申请号：US09294939
申请日：1999-04-19
IPC分类号： G06F1316
CPC分类号： G06F12/0804
摘要： A hazard control circuit for a cache controller that prevents overwriting of modified cache data without write back. The cache controller controls a non-blocking, N-way set associative cache that uses a write-back cache-coherency protocol. The hazard control circuit prevents data loss by deferring assignment until after completion of a pending fill for that way. The hazard control circuit of the present invention includes a transit hazard buffer, a stall assertion circuit and a way assignment circuit.
摘要翻译： 用于缓存控制器的危险控制电路，防止在不回写的情况下重写修改的高速缓存数据。 高速缓存控制器控制使用回写高速缓存一致性协议的非阻塞N路组关联高速缓存。 危险控制电路通过延迟分配来防止数据丢失，直到完成等待填充为止。 本发明的危害控制电路包括转接危险缓冲器，失速断言电路和方式分配电路。
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公开(公告)号：US06526485B1
公开(公告)日：2003-02-25
申请号：US09368008
申请日：1999-08-03
IPC分类号： G06F1200
CPC分类号： G06F9/3842 , G06F9/383 , G06F9/3861
摘要： Circuitry including a request queue and a bad address handling circuit. The request queue includes an entry for each outstanding load requesting access to a cache. Each request queue entry includes a valid bit, an issue bit and a flush bit. The state of the valid bit indicates whether or not the associated access request should be issued to the cache. The issue bit indicates whether the load access request has been issued to the cache and the flush bit indicates whether the data retrieved from the cache in response to the request should be loaded into a specified register. The bad address handling circuit responds to a replay load request by manipulating the states of the valid or flush bit of the relevant request queue entry to prevent completion of bad consumer load requests. The bad address handling circuit includes a validation circuit and a flush circuit. The validation circuit alters the state of the valid bit of the relevant request queue entry in response to the replay load request based upon the state of issue bit for that request queue entry. If the issue bit indicates that the load access request has not yet been issued to the cache, then the validation circuit alters the state of the associated valid bit to prevent the issuance of that load access request to the cache. On the other hand, if the bad consumer has already been issued to the cache, then the flush circuit responds by altering the state of the flush bit to prevent the data retrieved from the cache in response to the bad consumer from being loaded into the register file.
摘要翻译： 电路包括请求队列和不良地址处理电路。 请求队列包括每个未完成的负载请求访问高速缓存的条目。 每个请求队列条目包括有效位，发布位和刷新位。 有效位的状态指示是否应该向缓存发出关联的访问请求。 问题位指示加载访问请求是否已经发送到高速缓存，并且刷新位指示是否将响应于该请求从高速缓存检索的数据加载到指定的寄存器中。 坏地址处理电路通过操纵相关请求队列条目的有效或刷新位的状态来响应重放加载请求，以防止完成不良的消费者负载请求。 坏地址处理电路包括一个验证电路和一个冲洗电路。 响应于基于该请求队列条目的发布状态位的重放加载请求，验证电路改变相关请求队列条目的有效位的状态。 如果问题位指示加载访问请求尚未被发送到缓存，则验证电路改变相关联的有效位的状态，以防止向缓存发出该加载访问请求。 另一方面，如果坏消费者已经被发送到高速缓存，则刷新电路通过改变刷新位的状态来响应，以防止响应于坏消费者从缓存中检索的数据被加载到寄存器中 文件。
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公开(公告)号：US06408417B1
公开(公告)日：2002-06-18
申请号：US09376702
申请日：1999-08-17
IPC分类号： G11C2900
CPC分类号： G06F11/1064
摘要： On data writes to a cache memory in a digital data processing system, the existing data currently stored on the desired cache storage line is read out and parity checked. The read-out data is modified with new data only if there is no parity error. If a parity error is detected, a cache miss is signaled and the read-out line of data is written back into the cache memory with error correction code checking and error correction being performed on the defective line of data as part of this write-back to the cache memory.
摘要翻译： 在对数字数据处理系统中的高速缓冲存储器的数据写入时，读出当前存储在期望高速缓存存储线上的现有数据，并校验奇偶校验。 只有在没有奇偶校验错误的情况下，才能用新的数据修改读出的数据。 如果检测到奇偶校验错误，则发出高速缓存未命中，并且读出的数据行被写回到高速缓冲存储器中，其中错误校正码检查和错误校正是在缺陷数据行上执行的，作为该回写的一部分 到缓存内存。
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