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公开(公告)号：US10972109B2
公开(公告)日：2021-04-06
申请号：US16126722
申请日：2018-09-10
Applicant: Apple Inc.
Inventor： Somnath Kundu , Stefano Pellerano , Abhishek Agrawal
Abstract: A sub-sampler phase locked loop (SSPLL) system having a frequency locking loop (FLL) and a phase locked loop (PLL) is disclosed. The FLL is configured to detect frequency variations between a phase locked loop (PLL) output signal and a reference frequency and automatically generate a pulsed correction signal upon the detected frequency variations and apply the pulsed correction signal to a voltage controlled oscillator (VCO) control voltage. The PLL is configured to generate the PLL output signal based on the VCO control voltage.
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公开(公告)号：US10938396B2
公开(公告)日：2021-03-02
申请号：US16352043
申请日：2019-03-13
Applicant: Apple Inc.
Inventor： Abhishek Agrawal , Alon Cohen , Gil Horovitz , Somnath Kundu , Run Levinger , Stefano Pellerano , Jahnavi Sharma , Evgeny Shumaker , Izhak Hod
Abstract: A quadrature based voltage controlled oscillator (VCO) local oscillator (LO) system is disclosed. The system includes a phase detector, a quadrature phase VCO, a quadrature control path, an in-phase control path, and an in-phase VCO. The phase detector is configured to compare and generate phase error between a reference clock and an in-phase VCO output. The quadrature control path configured to generate a quadrature control voltage based on a quadrature VCO output and the in-phase VCO output. The quadrature phase VCO configured to generate the quadrature VCO output based on the quadrature control voltage and the generated phase error. The in-phase control path configured to generate an in-phase control voltage based on the quadrature VCO output and the in-phase VCO output. The in-phase VCO is configured to generate the in-phase VCO output based on the in-phase control voltage and the generated phase error. An all digital dual mode phase locked/phase tracking loop LO generate system is also disclosed.
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