公开(公告)号：US12079144B1

公开(公告)日：2024-09-03

申请号：US18054280

申请日：2022-11-10

Applicant: Apple Inc.

Inventor： Sebastian Werner ,  Amir Kleen ,  Jeonghee Shin ,  Peter A. Lisherness

IPC: G06F13/16 ,  G06F13/374

CPC classification number: G06F13/1642 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/374

Abstract: An apparatus includes a communication bus circuit, a memory circuit, a queue manager circuit, and an arbitration circuit. The communication bus circuit includes a command bus and a data bus separate from the command bus. The queue manager circuit may be configured to receive a first memory request and a second memory request, each request including a respective address value to be sent via the command bus. The first memory request may include a corresponding data operand to be sent via the data bus. The queue manager circuit may also be configured to distribute the first memory request and the second memory request among a plurality of bus queues. Distribution of the first and second memory requests may be based on the respective address values. The arbitration circuit may be configured to select a particular memory request from a particular one of the plurality of bus queues.