公开(公告)号：US11989131B2

公开(公告)日：2024-05-21

申请号：US18171565

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/0875 ,  G06F12/1027

CPC classification number: G06F12/0891 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/683

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.