公开(公告)号：US20230305965A1

公开(公告)日：2023-09-28

申请号：US18171565

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875

CPC classification number: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/683

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US20220066941A1

公开(公告)日：2022-03-03

申请号：US17008491

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875 ,  G06F30/39

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US20150049106A1

公开(公告)日：2015-02-19

申请号：US13970578

申请日：2013-08-19

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Sreevathsa Ramachandra ,  William V. Miller

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3824 ,  G06F9/3885

Abstract: Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.

Abstract translation: 公开了关于访问寄存器文件的请求的仲裁的技术。 在一个实施例中，装置包括写入队列和包括多个条目的寄存器文件。 在一个实施例中，设备被配置为基于多个请求特性从多个请求中选择请求，并将数据从接受的请求写入写入队列。 在一个实施例中，请求特征包括：请求是否是针对给定寄存器文件条目的代理的最后请求以及请求是否完成先前的请求。 在一个实施例中，最终仲裁器被配置为在给定周期中从写入队列，读取队列和多个执行管线的请求中选择访问寄存器文件的存储体。

公开(公告)号：US11989131B2

公开(公告)日：2024-05-21

申请号：US18171565

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/0875 ,  G06F12/1027

CPC classification number: G06F12/0891 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/1044 ,  G06F2212/683

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US09330432B2

公开(公告)日：2016-05-03

申请号：US13970578

申请日：2013-08-19

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  Sreevathsa Ramachandra ,  William V. Miller

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06T1/20

CPC classification number: G06T1/20 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3824 ,  G06F9/3885

Abstract: Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.

Abstract translation: 公开了关于访问寄存器文件的请求的仲裁的技术。 在一个实施例中，装置包括写入队列和包括多个条目的寄存器文件。 在一个实施例中，设备被配置为基于多个请求特性从多个请求中选择请求，并将数据从接受的请求写入写入队列。 在一个实施例中，请求特征包括：请求是否是针对给定寄存器文件条目的代理的最后请求以及请求是否完成先前的请求。 在一个实施例中，最终仲裁器被配置为在给定周期中从写入队列，读取队列和多个执行管线的请求中选择访问寄存器文件的存储体。

公开(公告)号：US11586551B2

公开(公告)日：2023-02-21

申请号：US17008491

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.