公开(公告)号：US20240312421A1

公开(公告)日：2024-09-19

申请号：US18673126

申请日：2024-05-23

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Pei-En Chang ,  Dongqi Zheng

IPC: G09G3/3266 ,  G09G3/3233 ,  G11C19/28

CPC classification number: G09G3/3266 ,  G11C19/28 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.