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公开(公告)号:US11861110B1
公开(公告)日:2024-01-02
申请号:US17956715
申请日:2022-09-29
Applicant: Apple Inc.
Inventor: Rungrot Kitsomboonloha , Donggeon Han , Jason N Gomez , Kyung Wook Kim , Nikolaus Hammler , Pei-En Chang , Saman Saeedi , Shih Chang Chang , Shinya Ono , Suk Won Hong , Szu-Hsien Lee , Victor H Yin , Young-Jik Jo , Yu-Heng Cheng , Joyan G Sanctis , Hongwoo Lee
CPC classification number: G06F3/04182 , G06F3/044 , H10K59/40 , G06F3/0412 , G06F2203/04107 , G06F2203/04112
Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.
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公开(公告)号:US20240420643A1
公开(公告)日:2024-12-19
申请号:US18654541
申请日:2024-05-03
Applicant: Apple Inc.
Inventor: Hao-Lin Chiu , Chin-Wei Lin , Shinya Ono , Kyung Wook Kim , Szu-Hsien Lee , Pei-En Chang , Kwang Soon Park
IPC: G09G3/3266 , H01L27/12 , H01L29/786
Abstract: A driver circuit configured to output a control signal to a row of display pixels is provided. The driver circuit can include a first transistor having a drain terminal coupled to a first positive power supply line, a gate terminal, and a source terminal that is coupled to an output port of the driver circuit on which the control signal is generated and a second transistor having a drain terminal coupled to the output port of the driver circuit, a gate terminal, and a source terminal that is coupled to a first ground power supply line. The first and second transistors can be coupled to a plurality of transistors coupled between a second positive power supply line and a second ground power supply line, configured to receive one or more clocks signals, and at least some of which include bottom gate terminals.
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公开(公告)号:US20240086014A1
公开(公告)日:2024-03-14
申请号:US18514934
申请日:2023-11-20
Applicant: Apple Inc.
Inventor: Rungrot Kitsomboonloha , Donggeon Han , Jason N Gomez , Kyung Wook Kim , Nikolaus Hammler , Pei-En Chang , Saman Saeedi , Shih Chang Chang , Shinya Ono , Suk Won Hong , Szu-Hsien Lee , Victor H Yin , Young-Jik Jo , Yu-Heng Cheng , Joyan G Sanctis , Hongwoo Lee
CPC classification number: G06F3/04182 , G06F3/044 , H10K59/40 , G06F3/0412 , G06F2203/04107 , G06F2203/04112
Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.
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公开(公告)号:US20240312421A1
公开(公告)日:2024-09-19
申请号:US18673126
申请日:2024-05-23
Applicant: Apple Inc.
Inventor: Shinya Ono , Chin-Wei Lin , Pei-En Chang , Dongqi Zheng
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
CPC classification number: G09G3/3266 , G11C19/28 , G09G3/3233 , G09G2300/0842 , G09G2310/0286 , G09G2310/0291 , G09G2310/08
Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.
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公开(公告)号:US11978385B2
公开(公告)日:2024-05-07
申请号:US17889242
申请日:2022-08-16
Applicant: Apple Inc.
Inventor: Yao Shi , Wei H Yao , Hyunwoo Nho , Jie Won Ryu , Kingsuk Brahma , Li-Xuan Chuo , Hyunsoo Kim , Myungjoon Choi , Ce Zhang , Alex H Pai , Shengkui Gao , Rungrot Kitsomboonloha , Shatam Agarwal , Vehbi Calayir , Chaohao Wang , Steven N Hanna , Pei-En Chang
IPC: G09G3/20
CPC classification number: G09G3/2096 , G09G3/2007 , G09G2310/0291 , G09G2320/0223 , G09G2320/0233 , G09G2330/021 , G09G2360/16
Abstract: This disclosure provides various techniques for providing fine-grain digital and analog pixel compensation to account for voltage error across an electronic display. By employing a two-dimensional digital compensation and a local analog compensation, a fine-grain and robust pixel compensation scheme may be provided to the electronic display.
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公开(公告)号:US10409118B1
公开(公告)日:2019-09-10
申请号:US15498356
申请日:2017-04-26
Applicant: Apple Inc.
Inventor: Pei-En Chang , Szu-Hsien Lee , Hsin-Ying Chiu , Chun-Yao Huang , Kyung Wook Kim , Shih Chang Chang , Hossein Nemati
IPC: G02F1/1343 , G02F1/1335 , G02F1/1333 , H01L27/32 , G02F1/133
Abstract: An electronic device may have a housing and a display in the housing. The display may have one or more curved edges such as curved edges associated with rounded corners in the display and housing. The display may have an array of pixels. The display may include full-strength pixels and may have a band of antialiasing pixels having selectively reduced strengths to visually smooth content displayed along the curved edges. The pixels may be organic light-emitting diode pixels, liquid crystal display pixels, or other display pixels. Organic light-emitting diode pixels may have drive transistors and associated organic light-emitting diodes. Selectively elevated series or opaque light blocking structures of selectively reduced areas may be used to selectively reduce the strength of the antialiasing pixels. Liquid crystal display pixels may include electrodes of different shapes and/or opaque layer openings of different sizes to form antialiasing pixels in desired patterns.
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公开(公告)号:US20180246363A1
公开(公告)日:2018-08-30
申请号:US15967441
申请日:2018-04-30
Applicant: Apple Inc.
Inventor: Hossein Nemati , Pei-En Chang , Yuan Chen , Tae Woon Cha , Sung H. Kim , Chia Hsuan Tai
IPC: G02F1/1343 , H01L27/12 , G02F1/1345 , G02F1/1362 , G02F1/1335
CPC classification number: G02F1/13439 , G02F1/133514 , G02F1/13454 , G02F1/136213 , G02F1/167 , G06F1/1652 , H01L27/1218
Abstract: An electronic device may have a housing and a display in the housing. The display may have one or more curved edges such as curved edges associated with rounded corners in the display and housing. The display may have an array of pixels. The display may include full-strength pixels and may have a band of antialiasing pixels having selectively reduced strengths to visually smooth content displayed along the curved edges. The antialiasing pixels may include single-opening pixels that each have a single opaque masking layer opening and may include dual-opening pixels that each include a pair of opaque masking layer openings. The single-opening pixels may be stronger than the dual-opening pixels.
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公开(公告)号:US11922887B1
公开(公告)日:2024-03-05
申请号:US17368472
申请日:2021-07-06
Applicant: Apple Inc.
Inventor: Shinya Ono , Chin-Wei Lin , Chuan-Jung Lin , Gihoon Choo , Hassan Edrees , Hei Kam , Jung Yen Huang , Pei-En Chang , Rungrot Kitsomboonloha , Szu-Hsien Lee , Zino Lee
IPC: G09G3/3275 , H10K59/121 , H10K59/126 , H10K59/131
CPC classification number: G09G3/3275 , H10K59/1213 , H10K59/1216 , H10K59/126 , H10K59/131 , G09G2320/0214
Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.
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公开(公告)号:US20230089942A1
公开(公告)日:2023-03-23
申请号:US17889242
申请日:2022-08-16
Applicant: Apple Inc.
Inventor: Yao Shi , Wei H Yao , Hyunwoo Nho , Jie Won Ryu , Kingsuk Brahma , Li-Xuan Chuo , Hyunsoo Kim , Myungjoon Choi , Ce Zhang , Alex H Pai , Shengkui Gao , Rungrot Kitsomboonloha , Shatam Agarwal , Vehbi Calayir , Chaohao Wang , Steven N Hanna , Pei-En Chang
IPC: G09G3/20
Abstract: This disclosure provides various techniques for providing fine-grain digital and analog pixel compensation to account for voltage error across an electronic display. By employing a two-dimensional digital compensation and a local analog compensation, a fine-grain and robust pixel compensation scheme may be provided to the electronic display.
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公开(公告)号:US20230014107A1
公开(公告)日:2023-01-19
申请号:US17749045
申请日:2022-05-19
Applicant: Apple Inc.
Inventor: Rungrot Kitsomboonloha , Chin-Wei Lin , Shinya Ono , Gihoon Choo , Hao-Lin Chiu , Kyung Wook Kim , Pei-En Chang , Szu-Hsien Lee , Zino Lee
IPC: G09G3/3225
Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.
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