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公开(公告)号：US09727944B2
公开(公告)日：2017-08-08
申请号：US14746034
申请日：2015-06-22
Applicant: Apple Inc.
Inventor： Andrew M. Havlir , Dzung Q. Vu , Liang Kai Wang
CPC classification number: G06T1/60 , G06F9/30145 , G06F9/3017 , G06F9/38 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3887 , G06F12/08 , G06F12/0875 , G06F2212/452 , G06T1/20 , Y02D10/13
Abstract: Techniques are disclosed relating to low-level instruction storage in a graphics unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the hazard circuitry is configured to generate hazard information that specifies dependencies between ones of the decoded graphics instructions in the same clause. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause and hazard information generated by the decode circuitry for the clause. This may reduce power consumption, in some embodiments, by reducing hazard checking when clauses are executed multiple times.
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公开(公告)号：US20210358078A1
公开(公告)日：2021-11-18
申请号：US17334139
申请日：2021-05-28
Applicant: Apple Inc.
Inventor： Andrew M. Havlir , Dzung Q. Vu , Liang Kai Wang
Abstract: Techniques are disclosed relating to low-level instruction storage in a processing unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause. A given clause may be fetched and executed multiple times, e.g., for different SIMD groups, while stored in the caching circuitry.
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公开(公告)号：US11023997B2
公开(公告)日：2021-06-01
申请号：US15657531
申请日：2017-07-24
Applicant: Apple Inc.
Inventor： Andrew M. Havlir , Dzung Q. Vu , Liang Kai Wang
Abstract: Techniques are disclosed relating to low-level instruction storage in a processing unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause. A given clause may be fetched and executed multiple times, e.g., for different SIMD groups, while stored in the caching circuitry.
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Patent Agency Ranking
公开(公告)号：US11954492B1
公开(公告)日：2024-04-09
申请号：US18054401
申请日：2022-11-10
Applicant: Apple Inc.
Inventor： Benjiman L. Goodman , Dzung Q. Vu , Robert Kenney
IPC: G06F9/38
CPC classification number: G06F9/3838 , G06F9/3836 , G06F9/3867 , G06F9/3887 , G06F9/3888
Abstract: Techniques are disclosed relating to channel stalls or deactivations based on the latency of prior operations. In some embodiments, a processor includes a plurality of channel pipelines for a plurality of channels and a plurality of execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may assign threads to channels and second scheduler circuitry may assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. Dependency circuitry may, for a first operation that depends on a prior operation that uses one of the execution pipelines, determine, based on status information for the prior operation from the one of the execution pipelines, whether to stall the first operation or to deactivate a thread that includes the first operation from its assigned channel.
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公开(公告)号：US20160371810A1
公开(公告)日：2016-12-22
申请号：US14746034
申请日：2015-06-22
Applicant: Apple Inc.
Inventor： Andrew M. Havlir , Dzung Q. Vu , Liang Kai Wang
CPC classification number: G06T1/60 , G06F9/30145 , G06F9/3017 , G06F9/38 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3887 , G06F12/08 , G06F12/0875 , G06F2212/452 , G06T1/20 , Y02D10/13
Abstract: Techniques are disclosed relating to low-level instruction storage in a graphics unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the hazard circuitry is configured to generate hazard information that specifies dependencies between ones of the decoded graphics instructions in the same clause. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause and hazard information generated by the decode circuitry for the clause. This may reduce power consumption, in some embodiments, by reducing hazard checking when clauses are executed multiple times.
Abstract translation: 公开了与图形单元中的低级指令存储有关的技术。 在一些实施例中，图形单元包括执行电路，解码电路，危险电路和高速缓存电路。 在一些实施例中，执行电路被配置为执行图形指令的子句。 在一些实施例中，解码电路被配置为接收图形指令和用于每个接收到的图形指令的子句标识符并对接收到的图形指令进行解码。 在一些实施例中，危险电路被配置为产生指定相同条款中的解码图形指令之间的依赖关系的危险信息。 在一些实施例中，高速缓存电路包括多个条目，每个条目被配置为存储在相同条款中的解码指令集合以及由该子句的解码电路产生的危险信息。 这在一些实施例中可以通过减少多次执行子句的危险检查来降低功耗。
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公开(公告)号：US20240095035A1
公开(公告)日：2024-03-21
申请号：US18054401
申请日：2022-11-10
Applicant: Apple Inc.
Inventor： Benjiman L. Goodman , Dzung Q. Vu , Robert Kenney
IPC: G06F9/38
CPC classification number: G06F9/3838 , G06F9/3867 , G06F9/3887
Abstract: Techniques are disclosed relating to channel stalls or deactivations based on the latency of prior operations. In some embodiments, a processor includes a plurality of channel pipelines for a plurality of channels and a plurality of execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may assign threads to channels and second scheduler circuitry may assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. Dependency circuitry may, for a first operation that depends on a prior operation that uses one of the execution pipelines, determine, based on status information for the prior operation from the one of the execution pipelines, whether to stall the first operation or to deactivate a thread that includes the first operation from its assigned channel.
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公开(公告)号：US11727530B2
公开(公告)日：2023-08-15
申请号：US17334139
申请日：2021-05-28
Applicant: Apple Inc.
Inventor： Andrew M. Havlir , Dzung Q. Vu , Liang Kai Wang
CPC classification number: G06T1/60 , G06F9/3017 , G06F9/30145 , G06F9/38 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3887 , G06F12/08 , G06T1/20 , G06F12/0875 , G06F2212/452 , Y02D10/00
Abstract: Techniques are disclosed relating to low-level instruction storage in a processing unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause. A given clause may be fetched and executed multiple times, e.g., for different SIMD groups, while stored in the caching circuitry.
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公开(公告)号：US20170323420A1
公开(公告)日：2017-11-09
申请号：US15657531
申请日：2017-07-24
Applicant: Apple Inc.
Inventor： Andrew M. Havlir , Dzung Q. Vu , Liang Kai Wang
CPC classification number: G06T1/60 , G06F9/30145 , G06F9/3017 , G06F9/38 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3887 , G06F12/08 , G06F12/0875 , G06F2212/452 , G06T1/20 , Y02D10/13
Abstract: Techniques are disclosed relating to low-level instruction storage in a processing unit. In some embodiments, a graphics unit includes execution circuitry, decode circuitry, hazard circuitry, and caching circuitry. In some embodiments the execution circuitry is configured to execute clauses of graphics instructions. In some embodiments, the decode circuitry is configured to receive graphics instructions and a clause identifier for each received graphics instruction and to decode the received graphics instructions. In some embodiments, the caching circuitry includes a plurality of entries each configured to store a set of decoded instructions in the same clause. A given clause may be fetched and executed multiple times, e.g., for different SIMD groups, while stored in the caching circuitry.
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