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    Method and apparatus for controlling cache line storage in cache memory
    2.
    发明授权
    Method and apparatus for controlling cache line storage in cache memory 有权

    公开(公告)号：US12124373B2

    公开(公告)日：2024-10-22

    申请号：US18185058

    申请日：2023-03-16

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David A. Roberts

    IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0846 ,  G06F12/0862

    CPC classification number: G06F12/0848 ,  G06F12/0815 ,  G06F12/0862 ,  G06F2212/282 ,  G06F2212/602 ,  G06F2212/621

    Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

    Processor instructions for data compression and decompression
    4.
    发明授权
    Processor instructions for data compression and decompression 有权

    公开(公告)号：US12106104B2

    公开(公告)日：2024-10-01

    申请号：US17133328

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Zhe Wang ,  Alaa R. Alameldeen ,  Christopher J. Hughes

    IPC: G06F9/30 ,  G06F12/0862 ,  H03M7/30

    CPC classification number: G06F9/30047 ,  G06F9/30145 ,  G06F12/0862 ,  H03M7/30 ,  G06F2212/602

    Abstract: A processor that includes compression instructions to compress multiple adjacent data blocks of uncompressed read-only data stored in memory into one compressed read-only data block and store the compressed read-only data block in multiple adjacent blocks in the memory is provided. During execution of an application to operate on the read-only data, one of the multiple adjacent blocks storing the compressed read-only block is read from memory, stored in a prefetch buffer and decompressed in the memory controller. In response to a subsequent request during execution of the application for an adjacent data block in the compressed read-only data block, the uncompressed adjacent block is read directly from the prefetch buffer.

    Replacement control for candidate producer-consumer relationships trained for prefetch generation
    9.
    发明授权
    Replacement control for candidate producer-consumer relationships trained for prefetch generation 有权

    公开(公告)号：US12045170B2

    公开(公告)日：2024-07-23

    申请号：US17545121

    申请日：2021-12-08

    Applicant: Arm Limited

    Inventor： Alexander Cole Shulyak ,  Karthik Sundaram

    IPC: G06F12/08 ,  G06F12/0862 ,  G06N20/00

    CPC classification number: G06F12/0862 ,  G06N20/00 ,  G06F2212/602

    Abstract: Prefetch generation circuitry generates requests to prefetch data to a cache, where the prefetch generation circuitry is configured to initiate a producer prefetch to request return of producer data having a producer address and to initiate at least one consumer prefetch to request prefetching of consumer data to the cache, the consumer data having an address derived from the producer data returned in response to the producer prefetch. Training circuitry updates, based on executed load operations, a training table indicating candidate producer-consumer relationships being trained for use by the prefetch generation circuitry in generating the producer/consumer prefetches. Replacement control circuitry controls replacement of candidate producer-consumer relationships based on a producer-data-consumer-operand (PD-CO) match-based replacement policy criterion, which depends on whether a PD-CO match condition, indicative of the producer data for a producer load matching an address operand of a consumer load, is satisfied for existing/new candidate producer-consumer relationships.

    PROVIDING MEMORY REGION PREFETCHING IN PROCESSOR-BASED DEVICES
    10.
    发明公开
    PROVIDING MEMORY REGION PREFETCHING IN PROCESSOR-BASED DEVICES 审中-公开

    公开(公告)号：US20240176742A1

    公开(公告)日：2024-05-30

    申请号：US18059076

    申请日：2022-11-28

    Applicant: QUALCOMM Incorporated

    Inventor： Suryanarayana Murthy Durbhakula

    IPC: G06F12/0862 ,  G06F12/0804 ,  G06F12/123

    CPC classification number: G06F12/0862 ,  G06F12/0804 ,  G06F12/123 ,  G06F2212/1024 ,  G06F2212/602

    Abstract: Providing memory region prefetching in processor-based devices is disclosed. In some aspects, a processor-based device comprises a region prefetcher circuit that comprises a plurality of access bitmaps corresponding to a plurality of contiguous memory regions of a system memory device. Each access bitmap comprises a plurality of bits corresponding to a plurality of memory blocks of a contiguous memory region. The region prefetcher circuit detects a memory access request to a memory block of a contiguous memory region, identifies an access bitmap corresponding to the contiguous memory region, and identifies a bit corresponding to the memory block. The region prefetcher circuit sets the bit to indicate the memory access request to the memory block. The region prefetcher circuit subsequently detects a prefetch trigger event, and, in response, identifies one or more unset bits of the access bitmap, and prefetches one or more memory blocks corresponding to the unset bits.

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