公开(公告)号：US20140164757A1

公开(公告)日：2014-06-12

申请号：US13913307

申请日：2013-06-07

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  James S. ISMAIL ,  Keith COX ,  Gaurav KAPOOR

IPC: G06F1/32

CPC classification number: G09G5/003 ,  G06F1/20 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T2200/28 ,  G09G5/18 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/127 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

Abstract translation: 本发明提供了一种用于针对包括在计算设备中的处理器的电压和/或频率进行目标缩放的技术。 一个实施例涉及基于每秒输入帧缓冲器的帧数来缩放处理器的电压/频率，以便减少或消除在计算设备的显示器上显示的动画中的笨拙。 本发明的另一实施例涉及基于GPU的利用率来缩放处理器的电压/频率，以便减少或消除由CPU向GPU缓慢发出指令所引起的任何瓶颈。 本发明的另一个实施例涉及根据由CPU执行的特定类型的指令来调整CPU的电压/频率。 另外的实施例包括在CPU执行具有传统台式/膝上型计算机应用的特征的工作负载时缩放CPU的电压和/或频率。

公开(公告)号：US20150128711A1

公开(公告)日：2015-05-14

申请号：US14472274

申请日：2014-08-28

Applicant: Apple Inc.

Inventor： James S. ISMAIL

IPC: G01P15/08

CPC classification number: G01H1/00 ,  G01P15/00

Abstract: The embodiments relate to the use of one or more phase lock loops (PLL's) for detecting wobble of a surface upon which a computing device is set. The PLL's can be configured to lock onto an exponentially-damped sinusoid output from an accelerometer in order to differentiate between surface-induced movement and direct human-induced movement of the computing device. Reduced latency in wobble detection can be achieved by implementing the PLL in software and using multiple PLL's per accelerometer axis. Further reduction in the latency of wobble detection can be achieved by seeding the phase of an oscillator signal generated by each PLL in order to improve phase estimates when attempting to lock a PLL onto the accelerometer output.

Abstract translation: 这些实施例涉及使用一个或多个锁相环（PLL）来检测设置有计算设备的表面的摆动。 PLL可以被配置为锁定来自加速度计的指数阻尼正弦曲线输出，以便区分表面引起的运动和计算设备的直接的人为的运动。 可以通过在软件中实现PLL并且在每个加速度计轴上使用多个PLL来实现摆动检测中减少的延迟。 摇摆检测的等待时间的进一步减少可以通过对由每个PLL产生的振荡器信号的相位进行接合来实现，以便在尝试将PLL锁定到加速度计输出时改善相位估计。

公开(公告)号：US20150348228A1

公开(公告)日：2015-12-03

申请号：US14821665

申请日：2015-08-07

Applicant: Apple Inc.

Inventor： John G. DORSEY ,  James S. ISMAIL ,  Keith COX ,  Gaurav KAPOOR

IPC: G06T1/20 ,  G09G5/18 ,  G09G5/00

CPC classification number: G09G5/003 ,  G06F1/20 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06T1/60 ,  G06T13/80 ,  G06T2200/28 ,  G09G5/18 ,  G09G2354/00 ,  G09G2360/08 ,  G09G2360/127 ,  Y02D10/126 ,  Y02D10/172

Abstract: The invention provides a technique for targeted scaling of the voltage and/or frequency of a processor included in a computing device. One embodiment involves scaling the voltage/frequency of the processor based on the number of frames per second being input to a frame buffer in order to reduce or eliminate choppiness in animations shown on a display of the computing device. Another embodiment of the invention involves scaling the voltage/frequency of the processor based on a utilization rate of the GPU in order to reduce or eliminate any bottleneck caused by slow issuance of instructions from the CPU to the GPU. Yet another embodiment of the invention involves scaling the voltage/frequency of the CPU based on specific types of instructions being executed by the CPU. Further embodiments include scaling the voltage and/or frequency of a CPU when the CPU executes workloads that have characteristics of traditional desktop/laptop computer applications.

Abstract translation: 本发明提供了一种用于针对包括在计算设备中的处理器的电压和/或频率进行目标缩放的技术。 一个实施例涉及基于每秒输入帧缓冲器的帧数来缩放处理器的电压/频率，以便减少或消除在计算设备的显示器上显示的动画中的笨拙。 本发明的另一实施例涉及基于GPU的利用率来缩放处理器的电压/频率，以便减少或消除由CPU向GPU缓慢发出指令所引起的任何瓶颈。 本发明的另一个实施例涉及根据由CPU执行的特定类型的指令来调整CPU的电压/频率。 另外的实施例包括在CPU执行具有传统台式/膝上型计算机应用的特征的工作负载时缩放CPU的电压和/或频率。