公开(公告)号：US12131032B1

公开(公告)日：2024-10-29

申请号：US17987899

申请日：2022-11-16

Applicant: Apple Inc.

Inventor： Li Rosenbaum ,  Elad Harush ,  Omri Flint

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0689 ,  G06F2212/7207

Abstract: A System on Chip (SoC) includes a processor, a parity generation circuit, and a dispatcher circuit. The processor is configured to produce store instructions for storing data blocks in a Non-Volatile-Memory (NVM). The parity generation circuit is configured to calculate parity blocks over the data blocks in accordance with a redundant storage scheme, to send the parity blocks to the NVM, and to produce completion notifications with respect to the parity blocks. The dispatcher circuit is configured to dispatch the store instructions to the NVM. The processor is further configured to send one or more parity-barrier instructions that specify synchronization barriers over the store instructions and the parity, and the dispatcher circuit is configured to dispatch the store instructions to the NVM in compliance with the parity-barrier instructions and the completion notifications.