公开(公告)号：US11899523B2

公开(公告)日：2024-02-13

申请号：US17933168

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3206

CPC classification number: G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US12131032B1

公开(公告)日：2024-10-29

申请号：US17987899

申请日：2022-11-16

Applicant: Apple Inc.

Inventor： Li Rosenbaum ,  Elad Harush ,  Omri Flint

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0689 ,  G06F2212/7207

Abstract: A System on Chip (SoC) includes a processor, a parity generation circuit, and a dispatcher circuit. The processor is configured to produce store instructions for storing data blocks in a Non-Volatile-Memory (NVM). The parity generation circuit is configured to calculate parity blocks over the data blocks in accordance with a redundant storage scheme, to send the parity blocks to the NVM, and to produce completion notifications with respect to the parity blocks. The dispatcher circuit is configured to dispatch the store instructions to the NVM. The processor is further configured to send one or more parity-barrier instructions that specify synchronization barriers over the store instructions and the parity, and the dispatcher circuit is configured to dispatch the store instructions to the NVM in compliance with the parity-barrier instructions and the completion notifications.

公开(公告)号：US20240184355A1

公开(公告)日：2024-06-06

申请号：US18438665

申请日：2024-02-12

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/3296 ,  G06F1/3206

CPC classification number: G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US20230059725A1

公开(公告)日：2023-02-23

申请号：US17933168

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US11467655B1

公开(公告)日：2022-10-11

申请号：US17340940

申请日：2021-06-07

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.