CLOCK/POWER-DOMAIN CROSSING CIRCUIT WITH ASYNCHRONOUS FIFO AND INDEPENDENT TRANSMITTER AND RECEIVER SIDES
    2.
    发明申请
    CLOCK/POWER-DOMAIN CROSSING CIRCUIT WITH ASYNCHRONOUS FIFO AND INDEPENDENT TRANSMITTER AND RECEIVER SIDES 审中-公开
    具有异步FIFO和独立发送器和接收端的时钟/电源域交叉电路

    公开(公告)号:US20160328182A1

    公开(公告)日:2016-11-10

    申请号:US14706076

    申请日:2015-05-07

    Applicant: Apple Inc.

    CPC classification number: G06F3/0656 G06F3/061 G06F3/0688 G06F13/4027

    Abstract: An electronic circuit includes transmit-side circuitry and receive-side circuitry. The transmit-side circuitry belongs to a first domain of the circuit and is configured to transmit a data signal from the first domain to a second domain of the circuit. The receive-side circuitry belongs to the second domain and is configured to receive the transmitted data signal. The receive-side circuitry is configured to transfer to the transmit-side circuitry a read pointer value indicative of a readout position in a buffer memory that buffers the data signal, and to retain the read pointer value in a non-volatile element that is accessible to the transmit-side circuitry.

    Abstract translation: 电子电路包括发射侧电路和接收侧电路。 发射侧电路属于电路的第一域,并且被配置为将数据信号从第一域发送到电路的第二域。 接收侧电路属于第二域,并被配置为接收发送的数据信号。 接收侧电路被配置为向发送侧电路传送指示缓冲存储器中的缓冲存储器中的读出位置的读指针值,并且将读指针值保持在可访问的非易失性元件中 发送侧电路。

Patent Agency Ranking