公开(公告)号：US10747535B1

公开(公告)日：2020-08-18

申请号：US15207115

申请日：2016-07-11

Applicant: Apple Inc.

Inventor： Mahesh K. Reddy ,  Matthew C. Stone

IPC: G06F9/30 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/084 ,  G06F12/0875

Abstract: Systems, apparatuses, and methods for processing load instructions are disclosed. A processor includes at least a data cache and a load queue for storing load instructions. The load queue includes poison indicators for load instructions waiting to reach non-speculative status. When a non-cacheable load instruction is speculatively executed, then the poison bit is automatically set for the load instruction. If a cacheable load instruction is speculatively executed, then the processor waits until detecting a first condition before setting the poison bit for the load instruction. The first condition may be detecting a cache line with data for the load instruction being evicted from the cache. If an ordering event occurs for a load instruction with a set poison bit, then the load instruction may be flushed and replayed. An ordering event may be a data barrier or a hazard on an older load targeting the same address as the load.

公开(公告)号：US11556485B1

公开(公告)日：2023-01-17

申请号：US17462416

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Jonathan Ying Fai Tong ,  Brett S. Feero ,  Christopher L. Colletti ,  David Edward Kroesche ,  Gagan Anand ,  Matthew C. Stone ,  So Min Song

IPC: G06F13/24 ,  G06F12/0879

Abstract: A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.