公开(公告)号：US20230305965A1

公开(公告)日：2023-09-28

申请号：US18171565

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875

CPC classification number: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875 ,  G06F2212/1044 ,  G06F2212/683

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US11586551B2

公开(公告)日：2023-02-21

申请号：US17008491

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

公开(公告)号：US11556485B1

公开(公告)日：2023-01-17

申请号：US17462416

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Jonathan Ying Fai Tong ,  Brett S. Feero ,  Christopher L. Colletti ,  David Edward Kroesche ,  Gagan Anand ,  Matthew C. Stone ,  So Min Song

IPC: G06F13/24 ,  G06F12/0879

Abstract: A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

公开(公告)号：US20220066941A1

公开(公告)日：2022-03-03

申请号：US17008491

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Sreevathsa Ramachandra ,  Christopher L. Colletti ,  David E. Kroesche

IPC: G06F12/0891 ,  G06F12/1027 ,  G06F12/0875 ,  G06F30/39

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.