公开(公告)号：US20230267168A1

公开(公告)日：2023-08-24

申请号：US17675369

申请日：2022-02-18

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan ,  Etai Zaltsman

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: Embodiments of the present disclosure relate to a vector circuit in an accelerator circuit for performing vector and scalar operations. The vector circuit reads a subset of instructions from an instruction memory, each instruction including an identification of at least a portion of a first vector and an identification of at least a portion of a second vector. The vector circuit further receives a portion of input data from a data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction on at least one first element of the first vector and at least one second element of the second vector to generate at least one output element of an output vector. Each instruction indicates positions in respective vectors for the at least one first element, the at least one second element and the at least one output element.

公开(公告)号：US11614937B1

公开(公告)日：2023-03-28

申请号：US17566193

申请日：2021-12-30

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan ,  Etai Zaltsman

IPC: G06F9/30

Abstract: Embodiments of the present disclosure relate to an accelerator circuit with a dynamic immediate values table (IVT). The accelerator circuit includes an instruction memory, a data memory, and a vector circuit with the IVT storing multiple immediate values at multiple entries. The vector circuit reads a subset of instructions from the instruction memory, each instruction including at least one corresponding pointer to at least one corresponding entry in the IVT. The vector circuit further receives a subset of input data from the data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction from the subset of instructions using a corresponding data vector of the received subset of input data identified in each instruction and at least one corresponding immediate value from the IVT pointed by the at least one corresponding pointer to generate corresponding output data.

公开(公告)号：US11914500B2

公开(公告)日：2024-02-27

申请号：US17591888

申请日：2022-02-03

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan

IPC: G06F9/48 ,  G06F11/36 ,  G06F11/00 ,  G06F9/44 ,  G06F9/46 ,  G06F9/32 ,  G06F9/30

CPC classification number: G06F11/3636 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/321 ,  G06F11/3656

Abstract: Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.

公开(公告)号：US20230281106A1

公开(公告)日：2023-09-07

申请号：US17591888

申请日：2022-02-03

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Danny Gal ,  Nir Nissan

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F11/3636 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/321 ,  G06F11/3656

Abstract: Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.