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公开(公告)号：US20240039576A1
公开(公告)日：2024-02-01
申请号：US17877503
申请日：2022-07-29
Applicant: Apple Inc.
Inventor： Omar E Elaasar , Aly Ismail
CPC classification number: H04B1/403 , H03D7/1466 , H03L7/099 , H03M1/66
Abstract: An electronic device may include wireless circuitry having a mixer configured to receive an oscillating signal from oscillator circuitry. The oscillator circuitry can include a chain of buffer circuits sometimes referred to as oscillator driver circuitry. Transformers may be coupled at the input and output of each buffer circuit in the chain. Adjustable biasing circuits may be formed at the input of a selected buffer circuit in the chain of the buffer circuits. The adjustable biasing circuits can be digital-to-analog converters (DACs). The adjustable biasing circuits may be configured to apply a differential direct current (DC) offset voltage to the input of the selected buffer circuit. The differential DC offset voltage can have a value chosen to minimize a second harmonic component of the oscillator driver circuitry. Configured and operated in this way, a second harmonic conversion gain of the mixer can be reduced and can improve the transmit and receive performance of the wireless circuitry.
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公开(公告)号：US20250105786A1
公开(公告)日：2025-03-27
申请号：US18473033
申请日：2023-09-22
Applicant: Apple Inc.
Inventor： Omar E Elaasar
Abstract: This disclosure is directed to a Voltage-Controlled Oscillator (VCO) with improved phase noise compared to other VCOs. The VCO may include a first cell and a second cell separated by common-mode (CM) isolation circuitry to reduce an amplitude of CM noise at an output signal. The CM isolation circuitry may inductively couple the first cell to the second cell for generating the output signal based on a resonant frequency range including resonant frequencies of the CM isolation circuitry, the first cell, and the second cell. As such, the first cell and the second cell may each include a portion of an entirety of the CM noise. In some cases, the portions of the CM noise on the first cell and/or the second cell may improve a signal to noise ratio of the output signal.
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公开(公告)号：US12052048B2
公开(公告)日：2024-07-30
申请号：US17877503
申请日：2022-07-29
Applicant: Apple Inc.
Inventor： Omar E Elaasar , Aly Ismail
CPC classification number: H04B1/403 , H03D7/1466 , H03L7/099 , H03M1/66
Abstract: An electronic device may include wireless circuitry having a mixer configured to receive an oscillating signal from oscillator circuitry. The oscillator circuitry can include a chain of buffer circuits sometimes referred to as oscillator driver circuitry. Transformers may be coupled at the input and output of each buffer circuit in the chain. Adjustable biasing circuits may be formed at the input of a selected buffer circuit in the chain of the buffer circuits. The adjustable biasing circuits can be digital-to-analog converters (DACs). The adjustable biasing circuits may be configured to apply a differential direct current (DC) offset voltage to the input of the selected buffer circuit. The differential DC offset voltage can have a value chosen to minimize a second harmonic component of the oscillator driver circuitry. Configured and operated in this way, a second harmonic conversion gain of the mixer can be reduced and can improve the transmit and receive performance of the wireless circuitry.
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公开(公告)号：US20240072735A1
公开(公告)日：2024-02-29
申请号：US17894065
申请日：2022-08-23
Applicant: Apple Inc.
Inventor： Omar E Elaasar
IPC: H03F1/32
CPC classification number: H03F1/3211 , H03F1/3205 , H03F2200/451
Abstract: An electronic device may include wireless circuitry having one or more differential circuits. A differential circuit can include first and second input transistors, first and second degeneration components, and first and second distortion cancellation transistors cross-coupled with the first and second input transistors. The first distortion cancellation transistor can be configured to sense a voltage at the first input transistor and to produce corresponding currents for cancelling a differential mode harmonic distortion current flowing through the second input transistor and for cancelling a common mode harmonic distortion current flowing through the first input transistor. The second distortion cancellation transistor can be configured to sense a voltage at the second input transistor and to produce corresponding currents for cancelling a differential mode harmonic distortion current flowing through the first input transistor and for cancelling a common mode harmonic distortion current flowing through the second input transistor.
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