公开(公告)号：US20130042074A1

公开(公告)日：2013-02-14

申请号：US13651943

申请日：2012-10-15

Applicant: Apple Inc.

Inventor： Sudarshan Kadambi ,  Puneet Kumar ,  Po-Yung Chang

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/383 ,  G06F2212/6028

Abstract: In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the processor of a dedicated prefetch instruction or hardware initiated via detection of a data cache miss by one or more load/store memory operations. The prefetch unit is further configured to generate prefetch requests responsive to the plurality of prefetch streams to prefetch data in to the data cache.