公开(公告)号：US11158650B2

公开(公告)日：2021-10-26

申请号：US16657583

申请日：2019-10-18

Applicant: Applied Materials, Inc.

Inventor： ChangSeok Kang ,  Tomohiko Kitajima

IPC: H01L23/48 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/67

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.