公开(公告)号：US20250040170A1

公开(公告)日：2025-01-30

申请号：US18738717

申请日：2024-06-10

Applicant: Applied Materials, Inc.

Inventor： Veeraraghavan S. BASKER ,  Gregory COSTRINI ,  Ashish PAL ,  Benjamin COLOMBEAU ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L29/775 ,  H01L21/762 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region via a cap layer, in recesses formed in portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into an inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate, the cap layers, and the STIs, forming selective cap layers at bottoms of the recesses, performing a substrate removal process to isotropically etch the substrate within the recesses, performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses, sculpting the spacer on sidewalls of the substrate and the STIs within the recesses, performing a cap layer removal process to remove the cap layers within the recesses, and forming metal contacts within the recesses.