公开(公告)号：US20250040170A1

公开(公告)日：2025-01-30

申请号：US18738717

申请日：2024-06-10

Applicant: Applied Materials, Inc.

Inventor： Veeraraghavan S. BASKER ,  Gregory COSTRINI ,  Ashish PAL ,  Benjamin COLOMBEAU ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L29/775 ,  H01L21/762 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region via a cap layer, in recesses formed in portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into an inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate, the cap layers, and the STIs, forming selective cap layers at bottoms of the recesses, performing a substrate removal process to isotropically etch the substrate within the recesses, performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses, sculpting the spacer on sidewalls of the substrate and the STIs within the recesses, performing a cap layer removal process to remove the cap layers within the recesses, and forming metal contacts within the recesses.

公开(公告)号：US20240332297A1

公开(公告)日：2024-10-03

申请号：US18595286

申请日：2024-03-04

Applicant: Applied Materials, Inc.

Inventor： Ashish PAL ,  El Mehdi BAZIZI ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66545

Abstract: A semiconductor structure forming a complementary field-effect transistor (CFET) includes a metal gate, a bottom field effect transistor (FET) module, the bottom FET module including a plurality of channel layers extending through the metal gate in a first direction, and a bottom source/drain (S/D) contact electrically connected to the plurality of channel layers via a bottom epitaxial (epi) S/D and a bottom interface, and a top FET module stacked on the bottom FET module in a second direction that is orthogonal to the first direction, the top FET module including a plurality of channel layers extending through the metal gate in the first direction, and a top source/drain (S/D) contact electrically connected to the plurality of channel layers via a top epitaxial (epi) S/D and a top interface, wherein the bottom S/D contact and the top S/D contact each comprise cobalt (Co) or tungsten (W).

公开(公告)号：US20230008858A1

公开(公告)日：2023-01-12

申请号：US17370835

申请日：2021-07-08

Applicant: Applied Materials, Inc.

Inventor： Ashish PAL ,  Yi ZHENG ,  El Mehdi BAZIZI

IPC: H01L29/06

Abstract: Embodiments of processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: depositing, via a first epitaxial growth process, an n-doped silicon material onto a substrate to form an n-doped layer while adjusting a ratio of dopant precursor to silicon precursor so that a dopant concentration of the n-doped layer increases from a bottom of the n-doped layer to a top of the n-doped layer; etching the n-doped layer to form a plurality of trenches having sidewalls that are tapered and a plurality of n-doped pillars therebetween; and filling the plurality of trenches with a p-doped material via a second epitaxial growth process to form a plurality of p-doped pillars.