公开(公告)号：US11088039B2

公开(公告)日：2021-08-10

申请号：US16151046

申请日：2018-10-03

Applicant: Applied Materials, Inc.

Inventor： Raman K. Nurani ,  Anantha R. Sethuraman ,  Koushik Ragavan ,  Karanpreet Aujla

IPC: G05B13/04 ,  H01L21/66 ,  H01L21/67 ,  G05B19/418

Abstract: Implementations described herein generally relate to improving silicon wafer manufacturing. In one implementation, a method includes receiving information describing a defect. The method further includes identifying a critical area of a silicon wafer and determining the probability of the defect occurring in the critical area. The method further includes determining, based on the probability, the likelihood of an open or a short occurring as a result of the defect occurring in the critical area. The method further includes providing, based on the likelihood, predictive information to a manufacturing system. In some embodiments, corrective action may be taken based on the predictive information in order to improve silicon wafer manufacturing.