SCALING FOR DIE-LAST ADVANCED IC PACKAGING
    1.
    发明公开

    公开(公告)号:US20240126180A1

    公开(公告)日:2024-04-18

    申请号:US18484016

    申请日:2023-10-10

    CPC classification number: G03F7/70508

    Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.

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