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    IMAGE STABILIZATION FOR DIGITAL LITHOGRAPHY
    1.
    发明申请
    IMAGE STABILIZATION FOR DIGITAL LITHOGRAPHY 有权

    公开(公告)号：US20250021016A1

    公开(公告)日：2025-01-16

    申请号：US18898943

    申请日：2024-09-27

    Applicant: Applied Materials, Inc.

    Inventor： Thomas L. LAIDIG ,  Christopher Dennis BENCHER

    IPC: G03F7/00

    Abstract: The present disclosure provides methods and systems for correcting the shooting of images from a spatial light modulator (SLM) to a substrate, when cross-scan vibrations, including sub-pixel cross-scan vibrations, are present. The methods and systems include shifting a mask pattern on an SLM rotated relative to the in-scan direction of travel on a substrate, shifting along an axis of the SLM to correct for cross-scan vibrations, and either delaying, or accelerating, the shooting of the mask pattern onto the substrate.

    RESERVING SPATIAL LIGHT MODULATOR SECTIONS TO ADDRESS FIELD NON-UNIFORMITIES
    2.
    发明申请
    RESERVING SPATIAL LIGHT MODULATOR SECTIONS TO ADDRESS FIELD NON-UNIFORMITIES 审中-公开

    公开(公告)号：US20200301288A1

    公开(公告)日：2020-09-24

    申请号：US16895971

    申请日：2020-06-08

    Applicant: Applied Materials, Inc.

    Inventor： Joseph R. JOHNSON ,  Thomas L. LAIDIG ,  Christopher Dennis BENCHER

    IPC: G03F7/20 ,  G03B27/70

    Abstract: Embodiments of the present disclosure generally provide improved photolithography systems and methods using a digital micromirror device (DMD). The DMD comprises columns and rows of micromirrors disposed opposite a substrate. Light beams reflect off the micromirrors onto the substrate, resulting in a patterned substrate. Certain subsets of the columns and rows of micromirrors may be positioned to the “off” position, such that they dump light, in order to correct for uniformity errors, i.e., features larger than desired, in the patterned substrate. Similarly, certain subsets of the columns and rows of micromirrors may be defaulted to the “off” position and selectively allowed to return to their programmed position in order to correct for uniformity errors, i.e., features smaller than desired, in the patterned substrate.

    FREEFORM DISTORTION CORRECTION
    3.
    发明申请
    FREEFORM DISTORTION CORRECTION 审中-公开

    公开(公告)号：US20180329310A1

    公开(公告)日：2018-11-15

    申请号：US15595497

    申请日：2017-05-15

    Applicant: Applied Materials, Inc.

    Inventor： Tamer COSKUN ,  Thomas L. LAIDIG ,  Jang Fung CHEN

    IPC: G03F7/20 ,  G03F7/00 ,  G03F1/70 ,  G03F1/36

    CPC classification number: G03F7/70433 ,  G03F1/36 ,  G03F1/70 ,  G03F7/0002 ,  G03F7/705 ,  G03F2007/2067

    Abstract: Methods and systems are provided that, in some embodiments, print and process a layer. The layer can be on a wafer or on an application panel. Thereafter, locations of the features that were actually printed and processed are measured. Based upon differences between the measured differences and designed locations for those features at least one distortion model is created. Each distortion model is inverted to create a corresponding correction model. When there are multiple sections, a distortion model and a correction model can be created for each section. Multiple correction models can be combined to create a global correction model.

    LITHOGRAPHY SYSTEM AND RELATED METHODS FOR FORMING STRUCTURES OF DIFFERENT DEPTHS AND SHAPES
    5.
    发明申请
    LITHOGRAPHY SYSTEM AND RELATED METHODS FOR FORMING STRUCTURES OF DIFFERENT DEPTHS AND SHAPES 有权

    公开(公告)号：US20250028251A1

    公开(公告)日：2025-01-23

    申请号：US18714792

    申请日：2022-11-09

    Applicant: Applied Materials, Inc.

    Inventor： Thomas L. LAIDIG ,  Chi-Ming TSAI

    IPC: G03F7/00 ,  G03F7/20

    Abstract: A method is provided including directing a plurality of beams of radiation at a first area of a first layer on a substrate, each beam incident upon a different portion of a plurality of portions within the first area. Each portion has an area of a first size, the plurality of beams of radiation are directed at the first area based on a first pattern, the first pattern comprises a plurality of unit cells that include a plurality of on cells and a plurality of off cells, each unit cell has an area smaller than the first size, the plurality of on cells identify locations within the first area at which a beam of radiation of the plurality of beams of radiation is centrally focused, and the plurality of off cells identify locations within the first area at which no beam of radiation of the plurality of beams of radiation is centrally focused.

    OVERLAYING ON LOCALLY DISPOSITIONED PATTERNS BY ML BASED DYNAMIC DIGITAL CORRECTIONS (ML-DDC)
    6.
    发明申请
    OVERLAYING ON LOCALLY DISPOSITIONED PATTERNS BY ML BASED DYNAMIC DIGITAL CORRECTIONS (ML-DDC) 有权

    公开(公告)号：US20230040198A1

    公开(公告)日：2023-02-09

    申请号：US17396453

    申请日：2021-08-06

    Applicant: Applied Materials, Inc.

    Inventor： Tamer COSKUN ,  Aidyn KEMELDINOV ,  Chung-Shin KANG ,  Uwe HOLLERBACH ,  Thomas L. LAIDIG

    IPC: G06F30/392 ,  H01L21/68 ,  G06N20/00

    Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

    FRUSTRATED CUBE ASSEMBLY
    8.
    发明申请
    FRUSTRATED CUBE ASSEMBLY 审中-公开

    公开(公告)号：US20180017781A1

    公开(公告)日：2018-01-18

    申请号：US15639600

    申请日：2017-06-30

    Applicant: Applied Materials, Inc.

    Inventor： David MARKLE ,  Thomas L. LAIDIG ,  Timothy N. THOMAS ,  Jang Fung CHEN

    IPC: G02B26/08 ,  G02B5/04 ,  G03F7/20 ,  G02F1/13

    CPC classification number: G02B26/0833 ,  G02B5/04 ,  G02F1/1303 ,  G03F7/7015 ,  G03F7/70275

    Abstract: The present disclosure generally relates to frustrated cube assemblies having a first prism having a first surface, a second surface, and a first hypotenuse, and a second prism having a third surface, a fourth surface, and a second hypotenuse. The first and second hypotenuses face one another and are separated by an air gap. The frustrated cube assembly may include a tilted mirror adjacent the second surface. The second surface may be a reflective diffraction grating. Light is reflected to a digital micromirror device (DMD) adjacent to the frustrated cube assembly at a normal incidence angle and through an image projection system along a single optical axis. The direction of light incident on the DMD is such that light reflected from an “on” mirror is directed along the normal to the DMD surface and at 45 degrees to the hypotenuses. The input and output light beams are parallel.

    OVERLAYING ON LOCALLY DISPOSITIONED PATTERNS BY ML BASED DYNAMIC DIGITAL CORRECTIONS (ML-DDC)
    9.
    发明公开
    OVERLAYING ON LOCALLY DISPOSITIONED PATTERNS BY ML BASED DYNAMIC DIGITAL CORRECTIONS (ML-DDC) 审中-公开

    公开(公告)号：US20240249062A1

    公开(公告)日：2024-07-25

    申请号：US18439287

    申请日：2024-02-12

    Applicant: Applied Materials, Inc.

    Inventor： Tamer COSKUN ,  Aidyn KEMELDINOV ,  Chung-Shin KANG ,  Uwe HOLLERBACH ,  Thomas L. LAIDIG

    IPC: G06F30/392 ,  G06N20/00 ,  H01L21/68

    CPC classification number: G06F30/392 ,  G06N20/00 ,  H01L21/68

    Abstract: Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

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