公开(公告)号：US20250118536A1

公开(公告)日：2025-04-10

申请号：US18484379

申请日：2023-10-10

Applicant: Applied Materials, Inc.

Inventor： Yi-Hsuan Hsiao ,  Dongqing Yang ,  Kelvin Chan ,  Philip A. Kraus ,  Thai Cheng Chua ,  Ping-Hwa Hsieh ,  Nitin K. Ingle

IPC: H01J37/32 ,  H01L21/311

Abstract: Semiconductor processing systems and methods for increased etch selectivity and rate are provided. Methods include etching a target material of a semiconductor substrate by flowing one or more plasma precursors through a microwave applicator into a remote plasma region of a semiconductor processing chamber. Generating a remote plasma within the remote plasma region at a microwave frequency, where the generated remote plasma comprises a density of greater than 1×1010 per cm3, an ion energy of less than or about 50 eV, or a combination thereof. Flowing the plasma effluents into a processing region of the semiconductor processing chamber. The microwave applicator includes a resonator body and a plate, where the resonator body is formed from or coated with a first dielectric material and the plate is formed from or coated with a second dielectric material.

公开(公告)号：US20240306391A1

公开(公告)日：2024-09-12

申请号：US18597057

申请日：2024-03-06

Applicant: Applied Materials, Inc.

Inventor： Hao-Ling Tang ,  Arvind Kumar ,  Mahendra Pakala ,  Keith Tatseun Wong ,  Yi-Hsuan Hsiao ,  Dongqing Yang ,  Mark Conrad ,  Rio Soedibyo ,  Minrui Yu

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: Two-dimensional (2D) materials formed in very thin layers improve the operation of semiconductor devices. However, forming a contact on 2D material tends to damage and penetrate the 2D material. A relatively gentle etch process has been developed that is very selective to the 2D material and allows vertical holes to be etched down to the 2D material without damaging or penetrating the 2D material. A low-power deposition process forms a protective liner when performing the metal fill to further prevent damage to the 2D material when forming the metal contacts in the holes. These processes allow a vertical metal contact to be formed on a planar 2D material or a vertical sidewall contact be formed in a 3D NAND without damaging the 2D material. This increases the contact area, reduces the contact resistance, and improves the performance of the 2D material in the device.