公开(公告)号：US6128666A

公开(公告)日：2000-10-03

申请号：US885000

申请日：1997-06-30

申请人： Shimon Muller ,  Louise Yeung ,  Ariel Hendel

发明人： Shimon Muller ,  Louise Yeung ,  Ariel Hendel

IPC分类号： H04L12/46 ,  H04L12/56 ,  H04L29/06 ,  H04J3/24 ,  G06F13/00 ,  H04J15/00

CPC分类号： H04L12/46 ,  H04L12/4645 ,  H04L12/467 ,  H04L49/103 ,  H04L69/22 ,  H04L49/3009 ,  H04L49/3036 ,  H04L49/354 ,  H04L49/602

摘要： A system and method for updating packet headers using hardware that maintains the high performance of the network element. In one embodiment, the system includes an input port process (IPP) that buffers the input packet received and forwards header information to the search engine. The search engine searches a database maintained on the switch element to determine the type of the packet. In one embodiment, the type may indicate whether the packet can be routed in hardware. In another embodiment, the type may indicate whether the packet supports VLANs. The search engine sends the packet type information to the IPP along with the destination address (DA) to be updated if the packet is to be routed, or a VLAN tag if the packet has been identified to be forwarded to a particular VLAN. The IPP, during transmission of the packet to a packet memory selectively replaces the corresponding fields, e.g., DA field or VLAN tag field; the modified packet is stored in the packet memory. Associated with the packet memory are control fields containing control field information conveyed to the packet memory by the IPP. An output port process (OPP) reads the modified input packet and the control field information and selectively performs additional modifications to the modified input packet and issue control signals to the output interface (i.e., MAC). The MAC, based upon the control signals, replaces the source address field with the address of the MAC and generates a CRC that is appended to the end of the packet.

摘要翻译： 一种用于使用维持网络元件的高性能的硬件来更新分组报头的系统和方法。 在一个实施例中，该系统包括缓冲所接收的输入分组的输入端口处理（IPP），并将头部信息转发到搜索引擎。 搜索引擎搜索在switch元素上维护的数据库以确定数据包的类型。 在一个实施例中，该类型可以指示分组是否可以在硬件中路由。 在另一个实施例中，该类型可以指示分组是否支持VLAN。 搜索引擎将分组类型信息与要进行路由的分组要更新的目标地址（DA）一起发送到IPP，如果分组已被标识为转发到特定VLAN，则将其发送到VLAN标签。 在将分组传输到分组存储器期间，IPP选择性地替换相应的字段，例如DA字段或VLAN标签字段; 修改的分组被存储在分组存储器中。 与分组存储器相关联的是包含由IPP传送到分组存储器的控制字段信息的控制字段。 输出端口处理（OPP）读取修改的输入分组和控制字段信息，并且选择性地对修改的输入分组执行附加修改，并向输出接口（即MAC）发出控制信号。 MAC基于控制信号，将源地址字段替换为MAC的地址，并生成附加到数据包末尾的CRC。

公开(公告)号：US5920566A

公开(公告)日：1999-07-06

申请号：US885114

申请日：1997-06-30

申请人： Ariel Hendel ,  Shimon Muller ,  William T. Zaumen ,  Louise Yeung

发明人： Ariel Hendel ,  Shimon Muller ,  William T. Zaumen ,  Louise Yeung

IPC分类号： H04L12/18 ,  H04L12/46 ,  H04L12/56 ,  H04J3/02

CPC分类号： H04L12/18 ,  H04L12/4645 ,  H04L45/00 ,  H04L45/60 ,  H04L49/602

摘要： A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers routing at wire-speed performance across subnetworks. Each subsystem includes a forwarding memory and an associated memory and is configured to identify unicast and multicast packets for routing purposes, modify the packets in hardware, including replace VLAN information, and forward the packets to the next hop. The routing decisions are made in the inbound subsystem, and packets are forwarded, if necessary given the network topology, through a separate outbound subsystem.

摘要翻译： 一种用于根据已知路由协议中继分组的多层分布式网元。 多个子系统的分布式架构通过子网提供线速性能的路由。 每个子系统包括转发存储器和相关联的存储器，并且被配置为识别用于路由目的的单播和多播分组，在硬件中修改分组，包括替换VLAN信息，并将分组转发到下一跳。 在入站子系统中进行路由决策，如果需要，通过单独的出站子系统转发数据包。

公开(公告)号：US5938736A

公开(公告)日：1999-08-17

申请号：US885116

申请日：1997-06-30

申请人： Shimon Muller ,  Ariel Hendel ,  Louise Yeung

发明人： Shimon Muller ,  Ariel Hendel ,  Louise Yeung

IPC分类号： G06F17/30 ,  H04L12/56 ,  H04L29/06 ,  G06F13/38 ,  G06F15/17

CPC分类号： H04L49/602 ,  H04L29/06 ,  H04L45/7453 ,  H04L49/201 ,  H04L49/205 ,  H04L49/3009 ,  H04L49/351 ,  H04L69/22

摘要： A multi-layer switch search engine architecture is provided. According to one aspect of the present invention, a switch fabric includes a search engine, and a packet header processing unit. The search engine may be coupled to a forwarding database memory and one or more input ports. The search engine is configured to schedule and perform accesses to the forwarding database memory and to transfer forwarding decisions to the one or more input ports. The header processing unit is coupled to the search engine and includes an arbitrated interface for coupling to the one or more input ports. The header processing unit is configured to receive a packet header from one or more of the input ports and is further configured to construct a search key for accessing the forwarding database memory based upon a predetermined portion of the packet header. The predetermined portion of the packet header is selected based upon a packet class with which the packet header is associated.

摘要翻译： 提供了多层交换机搜索引擎架构。 根据本发明的一个方面，交换结构包括搜索引擎和分组报头处理单元。 搜索引擎可以耦合到转发数据库存储器和一个或多个输入端口。 搜索引擎被配置为调度和执行对转发数据库存储器的访问并且将转发决定传送到一个或多个输入端口。 报头处理单元耦合到搜索引擎并且包括用于耦合到一个或多个输入端口的仲裁接口。 报头处理单元被配置为从一个或多个输入端口接收分组报头，并且还被配置为基于分组报头的预定部分构建用于访问转发数据库存储器的搜索关键字。 基于与分组报头相关联的分组类别来选择分组报头的预定部分。

公开(公告)号：US5909686A

公开(公告)日：1999-06-01

申请号：US885047

申请日：1997-06-30

申请人： Shimon Muller ,  Ariel Hendel ,  Louise Yeung ,  Leo Hejza ,  Shree Murthy

发明人： Shimon Muller ,  Ariel Hendel ,  Louise Yeung ,  Leo Hejza ,  Shree Murthy

IPC分类号： G06F17/30 ,  H04L12/56

CPC分类号： H04L49/3009 ,  G06F17/30557 ,  H04L49/254 ,  Y10S707/99931 ,  Y10S707/99945 ,  Y10S707/99948

摘要： A method and apparatus for providing hardware-assisted CPU access to a forwarding database is described. According to one aspect of the present invention, a switch fabric provides access to a forwarding database on behalf of a processor. The switch fabric includes a memory access interface configured to arbitrate access to a forwarding database memory. The switch fabric also includes a search engine coupled to the memory access interface and to multiple input ports. The search engine is configured to schedule and perform accesses to the forwarding database memory and to transfer forwarding decisions retrieved therefrom to the input ports. The switch fabric further includes command execution logic that is configured to interface with the processor for performing forwarding database accesses requested by the processor. According to another aspect of the invention one or more commands are provided to implement the following functions: (1) learning a supplied address; (2) reading associated data corresponding to a supplied search key; (3) aging forwarding database entries; (4) invalidating entries; (5) accessing mask data, such as mask data that may be stored in a mask per bit (MPB) content addressable memory (CAM), corresponding to a particular search key; (6) replacing forwarding database entries; and (7) accessing entries in the forwarding database.

摘要翻译： 描述了一种用于向转发数据库提供硬件辅助CPU访问的方法和装置。 根据本发明的一个方面，交换结构代表处理器提供对转发数据库的访问。 交换结构包括被配置为仲裁对转发数据库存储器的访问的存储器访问接口。 交换结构还包括耦合到存储器访问接口和多个输入端口的搜索引擎。 搜索引擎被配置为调度和执行对转发数据库存储器的访问，并将从其检索的转发决定传送到输入端口。 交换结构还包括命令执行逻辑，其被配置为与处理器接口以执行由处理器请求的转发数据库访问。 根据本发明的另一方面，提供一个或多个命令以实现以下功能：（1）学习所提供的地址; （2）读取与提供的搜索关键字对应的关联数据; （3）老化转发数据库条目; （4）使条目无效; （5）访问对应于特定搜索关键字的掩码数据，例如可能存储在每位掩码（MPB）内容可寻址存储器（CAM））中的掩码数据; （6）替换转发数据库条目; 和（7）访问转发数据库中的条目。

公开(公告)号：US6014380A

公开(公告)日：2000-01-11

申请号：US885257

申请日：1997-06-30

申请人： Ariel Hendel ,  Shimon Muller ,  Louise Yeung

发明人： Ariel Hendel ,  Shimon Muller ,  Louise Yeung

IPC分类号： H04L12/56 ,  H04L29/06

CPC分类号： H04L29/06 ,  H04L49/3009 ,  H04L49/25 ,  H04L49/351 ,  H04L49/354 ,  H04L69/22

摘要： A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers routing at wire-speed performance across subnetworks. Each subsystem includes a forwarding memory and an associated memory and is configured to identify unicast and multicast packets for routing purposes, modify the packets in hardware, including replace VLAN information, and forward the packets to the next hop. The routing decisions are made in the inbound subsystem, and packets and associated control information are forwarded, if necessary given the network topology, through a separate outbound subsystem. When packets traverse the internal links from one subsystem to another, encapsulation operations are conducted such as appending an additional cyclic redundancy code (CRC) to the packet before going through the internal link.

摘要翻译： 一种用于根据已知路由协议中继分组的多层分布式网元。 多个子系统的分布式架构通过子网提供线速性能的路由。 每个子系统包括转发存储器和相关联的存储器，并且被配置为识别用于路由目的的单播和多播分组，在硬件中修改分组，包括替换VLAN信息，并将分组转发到下一跳。 在入站子系统中进行路由决策，如果需要，通过单独的出站子系统转发数据包和相关控制信息。 当数据包穿过从一个子系统到另一个子系统的内部链路时，进行封装操作，例如在通过内部链路之前将附加的循环冗余码（CRC）附加到数据包。

公开(公告)号：US06873630B1

公开(公告)日：2005-03-29

申请号：US09314782

申请日：1999-05-19

申请人： Shimon Muller ,  Ariel Hendel

发明人： Shimon Muller ,  Ariel Hendel

IPC分类号： H04L12/40 ,  H04L12/28 ,  H04L12/413 ,  H04L29/06 ,  H04L29/08 ,  H04L12/56

CPC分类号： H04L29/06 ,  H04L69/14 ,  H04L69/323

摘要： An Ethernet architecture is provided for connecting a computer system or other network entity to a dedicated Ethernet network medium. The network interface enables the transmission and receipt of data by striping individual Ethernet frames across a plurality of logical channels and may thus operate at substantially the sum of the individual channel rates. Each channel may be conveyed by a separate conductor (e.g., in a bundle) or the channels may be carried simultaneously on a shared medium (e.g., an electrical or optical conductor that employs a form of multiplexing). On a sending station, a distributor within the sender's network interface receives Ethernet frames (e.g., from a MAC) and distributes frame bytes in a round-robin fashion on the plurality of channels. Each “mini-frame” is separately framed and encoded for transmission across its channel. On a receiving station, the receiver's network interface includes a collector for collecting the multiple mini-frames (e.g., after decoding) and reconstructing the frame's byte stream (e.g., for transfer to the receiver's MAC). The first and last bytes of each frame and mini-frame are marked for ease of recognition. Multiple unique idle symbols may be employed for transmission during inter-packet gaps to facilitate the collector's synchronization of the multiple channels and/or enhance error detection. A maximum channel skew is specified, and each received channel may be buffered with an elasticity that is proportional to the maximum skew so that significant propagation delay may be encountered between channels without disrupting communications.

摘要翻译： 提供了一种用于将计算机系统或其他网络实体连接到专用以太网网络介质的以太网架构。 网络接口通过跨多个逻辑信道划分单个以太网帧来实现数据的传输和接收，并且因此可以基本上以各个信道速率的总和来操作。 每个通道可以由单独的导体（例如，束）传送，或者可以在共享介质（例如采用多路复用形式的电或光导体）上同时携带通道。 在发送站上，发送者网络接口内的分发者接收以太网帧（例如，从MAC），并以循环方式在多个信道上分配帧字节。 每个“迷你帧”被单独成帧和编码以在其信道上传输。 在接收站，接收机的网络接口包括用于收集多个迷你帧（例如，在解码之后）并重构帧的字节流（例如，用于传送到接收机的MAC）的收集器。 每个帧和小帧的第一个和最后一个字节被标记为易于识别。 可以采用多个唯一的空闲符号来进行间隔间间隔期间的传输，以便收集器同步多个信道和/或增强错误检测。 指定最大信道偏移，并且每个接收信道可以以与最大偏移成比例的弹性来缓冲，使得可以在通道之间遇到显着的传播延迟而不中断通信。

公开(公告)号：US06246680B1

公开(公告)日：2001-06-12

申请号：US08884704

申请日：1997-06-30

申请人： Shimon Muller ,  Ariel Hendel ,  Howard Frazier

发明人： Shimon Muller ,  Ariel Hendel ,  Howard Frazier

IPC分类号： H04L1256

CPC分类号： H04L49/602 ,  H04L49/103 ,  H04L49/30 ,  H04L49/3027 ,  H04L49/351

摘要： An architecture for a highly integrated network element building block is provided. According to one aspect of the present invention, a network device building block includes a network interface with multiple ports for transmitting and receiving packets over a network. The network device building block also includes a packet buffer storage which is coupled to the network interface. The packet buffer storage acts as an elasticity buffer for adapting between incoming and outgoing bandwidth requirements. A shared memory manager may also be provided dynamically allocate and deallocate buffers in the packet buffer storage on behalf of the network interface and other clients of the packet buffer storage. The network device building block further includes a switch fabric which is coupled to the network interface. The switch fabric provides forwarding decisions for received packets. A given forwarding decision includes a list of ports upon which a particular received packet is to be forwarded. A central processing unit (CPU) interface is also included in the network device building block. The CPU interface is coupled to the switch fabric and is configured to forward packets received from the CPU based upon forwarding decisions provided by the switch fabric.

摘要翻译： 提供了一种高度集成的网络元件构建块的架构。 根据本发明的一个方面，网络设备构建块包括具有多个端口的网络接口，用于经由网络发送和接收分组。 网络设备构建块还包括耦合到网络接口的分组缓冲存储器。 分组缓冲存储器用作弹性缓冲器，用于适应进入和传出带宽要求。 还可以提供共享存储器管理器，代表分组缓冲存储器的网络接口和其他客户端动态地分配和释放分组缓冲存储器中的缓冲区。 网络设备构建块还包括耦合到网络接口的交换结构。 交换结构为接收到的数据包提供转发决策。 给定的转发决定包括要在其上转发特定接收分组的端口列表。 中央处理单元（CPU）接口也包括在网络设备构建块中。 CPU接口耦合到交换结构，并且被配置为基于由交换结构提供的转发决定来转发从CPU接收的分组。

公开(公告)号：US08762595B1

公开(公告)日：2014-06-24

申请号：US11098726

申请日：2005-04-05

申请人： Shimon Muller ,  Ariel Hendel ,  Yatin Gajjar ,  Michael Wong

发明人： Shimon Muller ,  Ariel Hendel ,  Yatin Gajjar ,  Michael Wong

IPC分类号： G06F13/14

CPC分类号： G06F13/385

摘要： A method for sharing a network interface among multiple hosts and includes providing a network interface, associating a first set of the plurality of memory access channels with a first host, and associating a second set of the plurality of memory access channels with a second host is disclosed. The network interface including a plurality of memory access channels.

摘要翻译： 一种用于在多个主机之间共享网络接口的方法，包括提供网络接口，将第一组多个存储器访问信道与第一主机相关联，以及将第二组多个存储器访问通道与第二主机相关联的方法是 披露 网络接口包括多个存储器访问信道。

公开(公告)号：US08023528B2

公开(公告)日：2011-09-20

申请号：US12691435

申请日：2010-01-21

申请人： Ariel Hendel ,  Michael Wong ,  Yatin Gajjar ,  Shimon Muller

发明人： Ariel Hendel ,  Michael Wong ,  Yatin Gajjar ,  Shimon Muller

IPC分类号： H04L12/66

CPC分类号： G06F15/17375

摘要： A method of resolving mutex contention within a network interface unit which includes providing a plurality of memory access channels, and moving a thread via at least one of the plurality of memory access channels, the plurality of memory access channels allowing moving of the thread while avoiding mutex contention when moving the thread via the at least one of the plurality of memory access channels is disclosed.

摘要翻译： 一种解决网络接口单元内的互斥竞争的方法，其包括提供多个存储器访问通道，以及经由所述多个存储器访问通道中的至少一个移动线程，所述多个存储器访问通道允许线程移动同时避免 公开了当通过多个存储器访问信道中的至少一个移动线程时的互斥争用。

公开(公告)号：US07567567B2

公开(公告)日：2009-07-28

申请号：US11098310

申请日：2005-04-05

申请人： Shimon Muller ,  Ariel Hendel ,  Yatin Gajjar ,  Michael Wong ,  Rahoul Puri ,  May Lin

发明人： Shimon Muller ,  Ariel Hendel ,  Yatin Gajjar ,  Michael Wong ,  Rahoul Puri ,  May Lin

IPC分类号： H04L12/28

CPC分类号： H04L47/10 ,  H04L45/745 ,  H04L47/2441 ,  H04L47/283 ,  H04L47/30 ,  H04L47/326 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9063

摘要： A network system which includes a plurality of processing entities, an interconnect device coupled to the plurality of processing entities, a memory system coupled to the interconnect device and the plurality of processing entities, a network interface unit coupled to the plurality of processing entities and the memory system via the interconnect device. The network interface includes a memory access module and a packet classifier. The memory access module includes a plurality of parallel memory access channels. The packet classifier provides a flexible association between packets and the plurality of processing entities via the plurality of memory access channels.

摘要翻译： 一种网络系统，其包括多个处理实体，耦合到所述多个处理实体的互连设备，耦合到所述互连设备和所述多个处理实体的存储器系统，耦合到所述多个处理实体的网络接口单元和 内存系统通过互连设备。 网络接口包括存储器访问模块和分组分类器。 存储器访问模块包括多个并行存储器存取通道。 分组分类器通过多个存储器访问信道提供分组与多个处理实体之间的灵活关联。