公开(公告)号：US20210055962A1

公开(公告)日：2021-02-25

申请号：US16546752

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Michael David ACHENBACH ,  Robert Greg MCDONALD ,  Nicholas Andrew PFISTER ,  Kelvin Domnic GOVEAS ,  Michael FILIPPO ,  . ABHISHEK RAJA ,  Zachary Allen KINGSBURY

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/50 ,  G06F9/52 ,  G06F9/30

Abstract: An apparatus and method are provided for operating an issue queue. The issue queue has a first section and a second section, where each of those sections comprises a number of entries, and where each entry is employed to store operation information identifying an operation to be performed by a processing unit. Allocation circuitry determines, for each item of received operation information, whether to allocate that operation information to an entry in the first section or to an entry in the second section. The operation information identifies not only the associated operation, but also each source operand required by the associated operation and availability of each source operand. Selection circuitry selects from the issue queue, during a given selection iteration, an operation to be issued to the processing unit, and selects that operation from amongst the operations whose required source operands are available. Availability update circuitry is used to update source operand availability for each entry whose operation information identifies as a source operand a destination operand of the selected operation in the given selection iteration. Further, a deferral mechanism is used to inhibit from selection by the selection circuitry, during at least a next selection iteration following the given selection iteration, any operation associated with an entry in the second section whose required source operands are now available due to that operation having as a source operand the destination operand of the selected operation in the given selection iteration. Such an approach can enable the effective capacity of the issue queue to be increased without adversely impacting the timing of the scheduling functionality performed in respect of the issue queue.

公开(公告)号：US20210026627A1

公开(公告)日：2021-01-28

申请号：US16521748

申请日：2019-07-25

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Michael FILIPPO ,  Huzefa Moiz SANJELIWALA ,  Kelvin Domnic GOVEAS

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Circuitry comprises an instruction decoder to decode a gather load instruction having a vector operand comprising a plurality of vector entries, in which each vector entry defines, at least in part, a respective address from which data is to be loaded; the instruction decoder being configured to generate a set of load operations relating to respective individual addresses in dependence upon the vector operand, each of the set of load operations having a respective identifier which is unique with respect to other load operations in the set, and control circuitry to maintain a data item for the gather load instruction, the data item including a count value representing a number of load operations in the set of load operations awaiting issue for execution; and execution circuitry to execute the set of load operations; the control circuitry being configured, in response to a detection from the count value of the data item associated with a given gather load instruction that the set of load operations generated for the given gather load instruction has reached a predetermined stage relative to execution of all of that set of load operations, to control handling of a consumer instruction, being an instruction which depends upon the completion of the given gather load instruction.

公开(公告)号：US20170293467A1

公开(公告)日：2017-10-12

申请号：US15093947

申请日：2016-04-08

Applicant: ARM LIMITED

Inventor： David Raymond LUTZ ,  Neil BURGESS ,  Kelvin Domnic GOVEAS

IPC: G06F5/01 ,  G06F9/30

CPC classification number: G06F5/015 ,  G06F7/483 ,  G06F9/30014 ,  G06F9/30025 ,  H03M7/24

Abstract: A data processing system 2 includes instruction decoder circuitry 12 responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry 28 performs a right shift upon at least part of the input number and left shifting circuitry 32 performs a left shift of at least part of the input number. Selection circuitry 38 serves to select one of the right shifted number and the left shifted number as a selected shifted number which forms at least part of the output number which is generated.