公开(公告)号：US20220179654A1

公开(公告)日：2022-06-09

申请号：US17114970

申请日：2020-12-08

Applicant: Arm Limited

Inventor： Vladimir Vasekin ,  David Michael Bull ,  Sanghyun Park ,  Alexei Fedorov

IPC: G06F9/38 ,  G06F9/30

Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.

公开(公告)号：US11366668B1

公开(公告)日：2022-06-21

申请号：US17114970

申请日：2020-12-08

Applicant: Arm Limited

Inventor： Vladimir Vasekin ,  David Michael Bull ,  Sanghyun Park ,  Alexei Fedorov

IPC: G06F9/38 ,  G06F9/30

Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.

公开(公告)号：US11416252B2

公开(公告)日：2022-08-16

申请号：US15855139

申请日：2017-12-27

Applicant: Arm Limited

Inventor： Vladimir Vasekin ,  Chiloda Ashan Senarath Pathirane ,  Jungsoo Kim ,  Alexei Fedorov

IPC: G06F9/30 ,  G06F9/38

Abstract: A data processing system includes an instruction pipeline containing instruction queue circuitry, fusion circuitry and decoder circuitry. The fusion circuitry serves to identify fusible groups of program instructions within a Y-wide window of program instructions and supply a stream of program instructions including such replacement fused program instructions to a X-wide decoder circuitry which decodes X program instructions in parallel using parallel decoders.

公开(公告)号：US11409532B1

公开(公告)日：2022-08-09

申请号：US17215429

申请日：2021-03-29

Applicant: Arm Limited

Inventor： Vladimir Vasekin ,  David Michael Bull ,  Sanghyun Park ,  Alexei Fedorov

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F9/32

Abstract: Apparatuses and methods of data processing are disclosed for processing circuitry having a pipeline of multiple stages. Value prediction storage circuitry holds value predictions, each associated with an instruction identifier. The value prediction storage circuitry performs look-ups and provides the processing circuitry with data value predictions. The processing circuitry speculatively issues a subsequent instruction into the pipeline by provisionally assuming that execution of a primary instruction will result in the generated data value prediction. Allocation of entries into the value prediction storage circuitry is based on a dynamic allocation policy, whereby likelihood of allocation into the value prediction storage circuitry of an data value prediction increases for an executed instruction when the executed instruction is associated with at least one empty processing stage in the pipeline.

公开(公告)号：US10719329B2

公开(公告)日：2020-07-21

申请号：US16021178

申请日：2018-06-28

Applicant: Arm Limited

Inventor： Vladimir Vasekin ,  David Michael Bull ,  Chiloda Ashan Senarath Pathirane ,  Alexei Fedorov

IPC: G06F9/38 ,  G06F21/64 ,  G06F9/30 ,  G06F9/54

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry. The request issued from the processing unit includes a signature value indicative of the predicted result value, and the result producing structure references the signature value in order to detect whether a mispredict condition exists indicating that the predicted result value differs from the result value. The apparatus further provides a mispredict signal transmission path via which the result producing structure, when the mispredict condition is detected, can assert a mispredict signal for receipt by the processing unit prior to the result value being available to the processing unit. Such an approach can reduce the misprediction penalty associated with using a mispredicted result value.