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公开(公告)号：US11947460B2
公开(公告)日：2024-04-02
申请号：US17729233
申请日：2022-04-26
Applicant: Arm Limited
Inventor： Vladimir Vasekin , David Michael Bull , Vincent Rezard , Anton Antonov
IPC: G06F12/08 , G06F9/38 , G06F12/0842 , G06F12/0891
CPC classification number: G06F12/0842 , G06F9/3816 , G06F12/0891 , G06F2212/1021
Abstract: Apparatus, method and code for fabrication of the apparatus, the apparatus comprising a cache providing a plurality of cache lines, each cache line storing a block of data; cache access control circuitry, responsive to an access request, to determine whether a hit condition is present in the cache; and cache configuration control circuitry to set, in response to a merging trigger event, merge indication state identifying multiple cache lines to be treated as a merged cache line to store multiple blocks of data, wherein when the merge indication state indicates that the given cache line is part of the merged cache line, the cache access control circuitry is responsive to detecting the hit condition to allow access to any of the data blocks stored in the multiple cache lines forming the merged cache line.
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公开(公告)号：US12292834B2
公开(公告)日：2025-05-06
申请号：US18343971
申请日：2023-06-29
Applicant: Arm Limited
Inventor： Vladimir Vasekin , Vincent Rezard , Antony John Penton , Cédric Denis Robert Airaud
IPC: G06F12/0862
Abstract: An apparatus comprises associating circuitry to associate an indirect prefetch condition with a memory access request when hint information indicates that the data to be accessed in response to the memory access request is address indicating data which is to be used to generate a second address for a subsequent memory access request. A second address can be generated using the address indicating data, and a prefetch memory access request can be issued to seek to make data at the second address available in the associated cache.
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公开(公告)号：US11194577B2
公开(公告)日：2021-12-07
申请号：US15571915
申请日：2016-04-11
Applicant: Arm Limited
Inventor： Antony John Penton , Simon John Craske , Vladimir Vasekin
Abstract: Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. Issue policy control circuitry (42) responds to a trigger event to enter a real time issue policy mode to control the issue circuitry (22) to issue candidate processing operations (such as program instruction, micro-operations, architecturally triggered processing operations etc.) to one of the non real time execution circuitry or the real time execution circuitry in dependence upon whether that candidate processing operation reads a register marked as a non real time dependent register.
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公开(公告)号：US11429393B2
公开(公告)日：2022-08-30
申请号：US14938285
申请日：2015-11-11
Applicant: ARM LIMITED
IPC: G06F9/38
Abstract: An apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to instructions which reference architectural registers using physical registers to store data values when performing the data processing operations. Mappings between the architectural registers and the physical registers are stored, and when a data hazard condition is identified with respect to out-of-order program execution of an instruction, an architectural register specified in the instruction is remapped to an available physical register. A reorder buffer stores an entry for each destination architectural register specified by the instruction, entries being stored in program order, and an entry specifies a destination architectural register and an original physical register to which the destination architectural register was mapped before the architectural register remapped to an available physical register.
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公开(公告)号：US20220179654A1
公开(公告)日：2022-06-09
申请号：US17114970
申请日：2020-12-08
Applicant: Arm Limited
Inventor： Vladimir Vasekin , David Michael Bull , Sanghyun Park , Alexei Fedorov
Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.
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Patent Agency Ranking
公开(公告)号：US11416252B2
公开(公告)日：2022-08-16
申请号：US15855139
申请日：2017-12-27
Applicant: Arm Limited
Inventor： Vladimir Vasekin , Chiloda Ashan Senarath Pathirane , Jungsoo Kim , Alexei Fedorov
Abstract: A data processing system includes an instruction pipeline containing instruction queue circuitry, fusion circuitry and decoder circuitry. The fusion circuitry serves to identify fusible groups of program instructions within a Y-wide window of program instructions and supply a stream of program instructions including such replacement fused program instructions to a X-wide decoder circuitry which decodes X program instructions in parallel using parallel decoders.
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公开(公告)号：US11409532B1
公开(公告)日：2022-08-09
申请号：US17215429
申请日：2021-03-29
Applicant: Arm Limited
Inventor： Vladimir Vasekin , David Michael Bull , Sanghyun Park , Alexei Fedorov
Abstract: Apparatuses and methods of data processing are disclosed for processing circuitry having a pipeline of multiple stages. Value prediction storage circuitry holds value predictions, each associated with an instruction identifier. The value prediction storage circuitry performs look-ups and provides the processing circuitry with data value predictions. The processing circuitry speculatively issues a subsequent instruction into the pipeline by provisionally assuming that execution of a primary instruction will result in the generated data value prediction. Allocation of entries into the value prediction storage circuitry is based on a dynamic allocation policy, whereby likelihood of allocation into the value prediction storage circuitry of an data value prediction increases for an executed instruction when the executed instruction is associated with at least one empty processing stage in the pipeline.
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公开(公告)号：US10719329B2
公开(公告)日：2020-07-21
申请号：US16021178
申请日：2018-06-28
Applicant: Arm Limited
Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry. The request issued from the processing unit includes a signature value indicative of the predicted result value, and the result producing structure references the signature value in order to detect whether a mispredict condition exists indicating that the predicted result value differs from the result value. The apparatus further provides a mispredict signal transmission path via which the result producing structure, when the mispredict condition is detected, can assert a mispredict signal for receipt by the processing unit prior to the result value being available to the processing unit. Such an approach can reduce the misprediction penalty associated with using a mispredicted result value.
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公开(公告)号：US09645824B2
公开(公告)日：2017-05-09
申请号：US13664659
申请日：2012-10-31
Applicant: ARM Limited
Inventor： Vladimir Vasekin , Allan John Skillman , Chiloda Ashan Senerath Pathirane , Jean-Baptiste Brelot
IPC: G06F9/38
CPC classification number: G06F9/3806
Abstract: An integrated circuit incorporates prefetch circuitry for prefetching program instructions from a memory. The prefetch circuitry includes a branch target address cache. The branch target address cache stores data indicative of branch target addresses of previously encountered branch instructions fetched from the memory. For each previously encountered branch instructions, the branch target address cache stores a tag value indicative of a fetch address of that previously encountered branch instruction. The tag values stored are generated by tag value generating circuitry which performs a hashing function upon a portion of the fetch address such that the tag value has a bit length less than the bit length of the portion of the fetch address concerned.
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公开(公告)号：US11366668B1
公开(公告)日：2022-06-21
申请号：US17114970
申请日：2020-12-08
Applicant: Arm Limited
Inventor： Vladimir Vasekin , David Michael Bull , Sanghyun Park , Alexei Fedorov
Abstract: A digital processor, method, and a non-transitory computer readable storage medium are described, and include a load pipeline operative to access a data content and convert the data content into a load result. The digital processor also includes a value prediction check circuit that is operative to access a speculative content, determine a predicted value from the speculative content, and determine a masked value by masking the data content with a data mask. The masked value is compared to the predicted value, and an action associated with the load result is commanded based upon the comparing of the masked value and the predicted value.
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