公开(公告)号：US11797307B2

公开(公告)日：2023-10-24

申请号：US17355641

申请日：2021-06-23

Applicant: Arm Limited

Inventor： Krishnendra Nathella ,  David Hennah Mansell ,  Alejandro Rico Carro ,  Andrew Mundy

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/12

CPC classification number: G06F9/3802 ,  G06F9/30047 ,  G06F9/3818 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/6028

Abstract: In response to an instruction decoder decoding a range prefetch instruction specifying first and second address-range-specifying parameters and a stride parameter, prefetch circuitry controls, depending on the first and second address-range-specifying parameters and the stride parameter, prefetching of data from a plurality of specified ranges of addresses into the at least one cache. A start address and size of each specified range is dependent on the first and second address-range-specifying parameters. The stride parameter specifies an offset between start addresses of successive specified ranges. Use of the range prefetch instruction helps to improve programmability and improve the balance between prefetch coverage and circuit area of the prefetch circuitry.