公开(公告)号：US11782845B2

公开(公告)日：2023-10-10

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Joseph Michael Pusdesris ,  Abhishek Raja ,  Karthik Sundaram ,  Anoop Ramachandra Iyer ,  Michael Brian Schinzler ,  James David Dundas ,  Yasuo Ishii

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.