公开(公告)号：US20240303156A1

公开(公告)日：2024-09-12

申请号：US18119389

申请日：2023-03-09

Applicant: Arm Limited

Inventor： Andrew David TUNE ,  Cyrille Nicolas DRAY

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F2201/82

Abstract: Data storage circuitry has entries to store data according to a data storage technology supporting non-destructive reads, each entry associated with an error checking code (ECC) and age indication. Scrubbing circuitry performs a patrol scrubbing cycle to visit each entry of the data storage circuitry within a scrubbing period. On a given visit to a given entry, the scrubbing operation comprises determining, based on the age indication associated with the given entry, whether a check-not-required period has elapsed for the given entry, and if so performing an error check on the data of the given entry using the ECC for that entry. The error check is omitted if the check-not-required period has not yet elapsed. The check-not-required period is restarted for a write target entry in response to a request causing an update to the data and the error checking code of the write target entry. The check-not-required period is restarted for a read target entry in response to a request causing the data of a read target entry to be non-destructively read and subject to the error check.

公开(公告)号：US20230307077A1

公开(公告)日：2023-09-28

申请号：US17704289

申请日：2022-03-25

Applicant: Arm Limited

Inventor： Siddharth GUPTA ,  Cyrille Nicolas DRAY ,  Luc Olivier PALAU ,  Sachin GULYANI ,  Antony John PENTON

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18 ,  G11C29/00

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/18 ,  G11C29/785 ,  G11C2029/1202

Abstract: An apparatus is provided having a memory device and associated access control circuitry, and an additional memory device and associated additional access control circuitry. Redundant data generation circuitry generates, for a given block of data having an associated given memory address, an associated block of redundant data for use in an error detection process. The access control circuitry is arranged to store, at a location in the memory device determined from the given memory address, at least a portion of the given block of data and a first copy of the associated block of redundant data, and the additional access control circuitry is arranged to store, at a location in the additional memory device determined from the given memory address, any remaining portion of the given block of data not stored in the memory device and a second copy of the associated block of redundant data. Error detection circuitry performs the error detection process on the stored given block of data using one copy of the associated block of redundant data, and generates an output signal indicating a result of the error detection process. Comparison circuitry compares the first and second copies of the associated block of redundant data, and generates a comparison result signal to supplement the output signal from the error detection circuitry.