公开(公告)号：US20170185516A1

公开(公告)日：2017-06-29

申请号：US14980144

申请日：2015-12-28

Applicant: ARM Limited

Inventor： Ashley Miles STEVENS ,  Andrew David TUNE ,  Daniel Adam SARA

IPC: G06F12/08 ,  G06F9/30 ,  G06F15/80 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F2212/1048

Abstract: A data processing apparatus having an interconnect circuit operable to transfer snoop messages between a plurality of connected devices, at least one of which has multiple ports each coupled to a local cache. The interconnect circuit has decode logic that identifies, from an address in a snoop message, which port is coupled to the local cache associated with the address, and the interconnect circuit transmits the snoop message to that port. The interconnect circuit may also have a snoop filter that stores a snoop vector for each block of data in the local caches. Each snoop vector has an address tag that identifies the block of data and a presence vector indicative of which devices of the connected devices have a copy of the block of data. The presence vector does not identify which port of a device has access to the copy.

公开(公告)号：US20160062890A1

公开(公告)日：2016-03-03

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Jamshed JALAL ,  Mark David WERKHEISER ,  Arthur LAUGHTON ,  George Robert Scott LLOYD ,  Peter Andrew RIOCREUX ,  Daniel SARA

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。

公开(公告)号：US20200301837A1

公开(公告)日：2020-09-24

申请号：US16361548

申请日：2019-03-22

Applicant: Arm Limited

Inventor： Andrew David TUNE

IPC: G06F12/0817 ,  G06F12/0882

Abstract: A data processing system comprises a requesting node; a home node to control coherency amongst data stored by the data processing system; and one or more further nodes, at least one of the further nodes having a memory; the requesting node being configured to issue a data handling transaction to the home node, the data handling transaction defining a data handling operation relating to a range of memory addresses, the requesting node being configured to maintain an address hazard at the requesting node inhibiting issue of another data handling transaction for that range of memory addresses until the requesting node is notified by the home node that the data handling transaction has completed; the home node being configured, in response to the data handling transaction, to issue one or more data handling instructions to cause one or more given nodes of the one or more further nodes to perform the data handling operation, the home node being configured to notify completion to the requesting node in response to the issue of the one or more data handling instructions to the one or more given nodes.

公开(公告)号：US20200026461A1

公开(公告)日：2020-01-23

申请号：US16037091

申请日：2018-07-17

Applicant: Arm Limited

Inventor： Andrew David TUNE

IPC: G06F3/06 ,  G06F12/06

Abstract: An integrated circuit comprises: a requesting node to issue a data access request specifying a target address and an enable vector comprising a plurality of enable indications each indicating whether a respective portion of a target address range starting at the target address is an active portion or an inactive portion, and a control node responsive to the data access request to control at least one destination node to service at least one data access transaction. Each data access transaction is associated with a respective portion of the target address range indicated as an active portion by the enable vector of the data access request.

公开(公告)号：US20160055085A1

公开(公告)日：2016-02-25

申请号：US14467469

申请日：2014-08-25

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Daniel SARA

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F2212/1016 ,  G06F2212/621

Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.

Abstract translation: 互连具有用于实施一组数据访问事务的排序的事务跟踪电路，使得它们以从主设备接收的顺序被发布到从设备。 交易跟踪电路被重新用于执行由一组数据访问事务触发的窥探事务的排序，用于窥探由窥探过滤器识别的主设备作为事务的目标地址的缓存数据。

公开(公告)号：US20150301961A1

公开(公告)日：2015-10-22

申请号：US14628331

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Daniel SARA ,  Sean James SALISBURY ,  Arthur LAUGHTON ,  Peter Andrew RIOCREUX

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/1673

Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialisation checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

Abstract translation: 系统对核心集成电路2包括将多个事务源连接到多个事务目的地的互连电路4。 互连电路4包括用于缓冲访问事务的重新排序缓冲器和用于执行诸如点序列化检查和标识符重用检查的危险检查的危险检查电路46,48,50,52。 检查抑制电路62,64,66,68用于根据一个或多个状态变量来抑制一个或多个危险检查，所述一个或多个状态变量本身依赖于非危险检查或不被抑制的访问事务以外的访问事务。 作为示例，如果知道当前没有其他访问事务在重新排序缓冲器26内缓冲，或者替代地没有来自在重排序缓冲器26内缓冲的相同事务源的其他访问事务，则可以抑制危险检查。

公开(公告)号：US20140372696A1

公开(公告)日：2014-12-18

申请号：US13920685

申请日：2013-06-18

Applicant: ARM Limited

Inventor： Andrew David TUNE ,  Sean James Salisbury

IPC: G06F3/06

CPC classification number: G06F12/0864 ,  G06F12/0846

Abstract: A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways.

Abstract translation: 数据阵列有多种方式，每种方式都有用于存储数据值的条目。 响应于写请求，具有目标地址的更新的数据值可以存储在包括从每个方式基于目标地址选择的条目的对应的一组条目中的任何一个中。 更新队列存储表示待决写入请求的更新信息。 对于与不同方式相对应的一组待决写入请求，从更新队列中选择更新信息，并且并行执行这些写入请求，使得更新的值被写入不同方式的条目。

公开(公告)号：US20240303156A1

公开(公告)日：2024-09-12

申请号：US18119389

申请日：2023-03-09

Applicant: Arm Limited

Inventor： Andrew David TUNE ,  Cyrille Nicolas DRAY

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F2201/82

Abstract: Data storage circuitry has entries to store data according to a data storage technology supporting non-destructive reads, each entry associated with an error checking code (ECC) and age indication. Scrubbing circuitry performs a patrol scrubbing cycle to visit each entry of the data storage circuitry within a scrubbing period. On a given visit to a given entry, the scrubbing operation comprises determining, based on the age indication associated with the given entry, whether a check-not-required period has elapsed for the given entry, and if so performing an error check on the data of the given entry using the ECC for that entry. The error check is omitted if the check-not-required period has not yet elapsed. The check-not-required period is restarted for a write target entry in response to a request causing an update to the data and the error checking code of the write target entry. The check-not-required period is restarted for a read target entry in response to a request causing the data of a read target entry to be non-destructively read and subject to the error check.

公开(公告)号：US20190361486A1

公开(公告)日：2019-11-28

申请号：US15989228

申请日：2018-05-25

Applicant: Arm Limited

Inventor： Saira Samar MALIK ,  David Joseph HAWKINS ,  Andrew David TUNE ,  Guanghui GENG ,  Julian Jose Hilgemberg PONTES

IPC: G06F1/12 ,  G06F17/50

Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.

公开(公告)号：US20180173660A1

公开(公告)日：2018-06-21

申请号：US15384688

申请日：2016-12-20

Applicant: ARM Limited

Inventor： Guanghui GENG ,  Andrew David TUNE ,  Daniel Adam SARA ,  Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL

IPC: G06F13/364 ,  G06F13/42 ,  G06F13/40 ,  G06F12/0888 ,  G06F12/0815

CPC classification number: G06F13/364 ,  G06F12/0815 ,  G06F12/0888 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/6046 ,  G06F2212/621

Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.