公开(公告)号：US20200073660A1

公开(公告)日：2020-03-05

申请号：US16118528

申请日：2018-08-31

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Cedric Denis Robert AIRAUD ,  Luca NASSI ,  Damien Robin MARTIN

IPC: G06F9/30 ,  G06F5/01

Abstract: Apparatus comprises counter and bit-shift circuitry to provide a succession of processing stages each comprising a count operation stage and a corresponding bit-shift stage, each processing stage operating with respect to a set of contiguous n-bit groups of bit positions, where n is 1 for a first processing stage and n doubles from one processing stage in the succession of processing stages to a next processing stage in the succession of processing stages; each count operation stage being configured to generate, for a first set of alternate instances of the n-bit groups of bit positions, count values indicating a respective number of bits of a predetermined bit value in a mask data word; and each bit-shift stage being configured to generate a bit-shifted data word by bit-shifting bits of a data word to be processed, for a second set of alternate instances of the n-bit groups of bit positions complementary to the first set, by respective numbers of bit positions dependent upon the count values generated by the respective count operation stage, in which the bit-shifted data word for one bit-shift stage in the succession of processing stages is used as the data word to be processed by the next bit-shift stage in the succession of processing stages.

公开(公告)号：US20190377706A1

公开(公告)日：2019-12-12

申请号：US16005790

申请日：2018-06-12

Applicant: Arm Limited

Inventor： Cedric Denis Robert AIRAUD ,  Luca NASSI ,  Damien Robin MARTIN ,  Xiaoyang SHEN

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30 ,  G06F1/32

Abstract: Apparatuses and methods of data processing are disclosed. An apparatus comprises two data processing clusters each having multiple data processing lanes to perform single instruction multiple data (SIMD) processing. Decoded instructions are issued to at least one of the two data processing clusters. A decoded SIMD instruction specifying a vector length which is more than the width of the data processing lanes of the first data processing cluster has a first part issued to the first data processing cluster for execution. An issuance target for a second remaining part of the decoded SIMD instruction is selected in dependence on a dynamic performance condition. When the dynamic performance condition has a first state the issuance target is the first data processing cluster and when the dynamic performance condition has a second state the issuance target is the second data processing cluster. When the issuance target is the first data processing cluster, to schedule the first and second parts of the decoded SIMD instruction in series.

公开(公告)号：US20200065109A1

公开(公告)日：2020-02-27

申请号：US16524667

申请日：2019-07-29

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Damien Robin MARTIN ,  Cédric Denis Robert AIRAUD ,  Luca NASSI ,  François DONATI

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/355 ,  G06F9/22

Abstract: An apparatus has a processing pipeline, and first and second register files. A temporary-register-using instruction is supported which controls the pipeline to perform an operation using a temporary variable derived from an operand stored in the first register file. In response to the instruction, when a predetermined condition is not satisfied, the pipeline processes at least one register move micro-operation to transfer data from the at least one source register of the first register file to at least one newly allocated temporary register of the second register file. When the condition is satisfied, the operation can be performed using a temporary variable already stored in the temporary register of the second register file used by an earlier temporary-register-using instruction specifying the same source register for determining the temporary variable, in the absence of an intervening instruction for rewriting the source register.

公开(公告)号：US20190303265A1

公开(公告)日：2019-10-03

申请号：US16063802

申请日：2015-12-22

Applicant: ARM LIMITED

Inventor： Damien Robin MARTIN ,  Clément Marc DEMONGEOT ,  Michael John WILLIAMS

IPC: G06F11/36 ,  G06F9/38 ,  G06F9/30 ,  G06F9/52

Abstract: A method, apparatus and system are provided for diagnosing a processor executing a stream of instructions by causing the processor to execute the stream of instructions in a sequence of stages with a diagnostic exception being taken between each stage. The method involves controlling the processor in a current stage, when a point is reached where the diagnostic exception is to be taken, to store in a storage location type indicator information comprising a type indicator for a current instruction in the stream and a type indicator for a next instruction in the stream. The diagnostic exception is then taken, causing a diagnostic operation to be performed which includes accessing the type indicator information from the storage location and, dependent on the type indicator for the current instruction and the type indicator for the next instruction, determining control information to identify at least one trigger condition for a next diagnostic exception. Thereafter, return from the diagnostic exception causes the processor to operate in a next stage in accordance with the determined control information. By capturing information not only about the current instruction being processed at the point that the diagnostic exception is to be taken, but also information about the next instruction, this can provide a significant improvement in the efficiency of the handling of the diagnostic process.