公开(公告)号：US11636048B2

公开(公告)日：2023-04-25

申请号：US17259785

申请日：2019-06-07

Applicant: Arm Limited

Inventor： Richard Roy Grisenthwaite ,  Graeme Peter Barnes

IPC: G06F12/14 ,  G06F11/07 ,  G06F11/14 ,  G06F12/1027

Abstract: An apparatus comprising memory access circuitry to perform a tag-guarded memory access in response to a received target address and methods of operation of the same are disclosed. In the tag-guarded memory access a guard-tag retrieval operation seeks to retrieve a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the received target address, and a guard-tag check operation compares an address tag associated with the received target address with the guard tag retrieved by the guard-tag retrieval operation. When the guard-tag retrieval operation is unsuccessful in retrieving the guard tag, a substitute guard tag value is stored as the guard tag in association with the block of one or more memory locations comprising the addressed location identified by the target address.

公开(公告)号：US11573907B2

公开(公告)日：2023-02-07

申请号：US17269388

申请日：2019-10-21

Applicant: Arm Limited

Inventor： Ruben Borisovich Ayrapetyan ,  Graeme Peter Barnes ,  Richard Roy Grisenthwaite

IPC: G06F12/1027 ,  G06F12/14

Abstract: An apparatus and method are provided for controlling memory accesses. The apparatus has memory access circuitry for performing a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag. Further, the apparatus has control tag storage for storing, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region. Each memory region corresponds to multiple of the blocks. This provides a very flexible and efficient mechanism for performing tag-guarded memory access operations.

公开(公告)号：US11030344B2

公开(公告)日：2021-06-08

申请号：US16073497

申请日：2016-12-23

Applicant: ARM LIMITED

Inventor： Graeme Peter Barnes ,  Richard Roy Grisenthwaite

IPC: G06F21/64 ,  G06F21/52 ,  G06F21/12 ,  G06F12/14 ,  G06F21/60

Abstract: An apparatus and method are provided for controlling use of bounded pointers. The apparatus includes storage to store bounded pointers, where each bounded pointer comprises a pointer value and associated attributes, with the associated attributes including range information indicative of an allowable range of addresses when using the pointer value. Processing circuitry is used to perform a signing operation on an input bounded pointer in order to generate an output bounded pointer in which a signature generated by the signing operation is contained within the output bounded pointer in place of specified bits of the input bounded pointer. In addition, the associated attributes include signing information which is set by the processing circuitry within the output bounded pointer to identify that the output bounded pointer has been signed. Such an approach provides increase resilience to control flow integrity attack when using bounded pointers.

公开(公告)号：US11307856B2

公开(公告)日：2022-04-19

申请号：US16971755

申请日：2019-02-13

Applicant: Arm Limited

Inventor： Graeme Peter Barnes ,  Richard Roy Grisenthwaite

IPC: G06F9/30 ,  G06F9/32

Abstract: An apparatus (2) comprises an instruction decoder (6) and processing circuitry (4). The instruction decoder (6) supports branch instructions for triggering a non-sequential change of program flow to an instruction at a target address, including: a branch-with-link instruction for which a return address is set for a subsequent return of program flow; and at least one target-checking type of branch instruction, for which when the branch is taken an error handling response is triggered when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction. For at least a subset of the at least one target-checking type of branch instruction, a branch target variant of the branch-with-link instruction is a permitted type of branch target instruction.

公开(公告)号：US11119925B2

公开(公告)日：2021-09-14

申请号：US16609298

申请日：2018-04-19

Applicant: Arm Limited

Inventor： Stuart David Biles ,  Graeme Peter Barnes

IPC: G06F12/0815 ,  G06F16/907 ,  G06F9/38 ,  G06F9/46 ,  G06F12/0811

Abstract: Apparatus comprising cache storage and a method of operating such a cache storage are provided. Data blocks in the cache storage have capability metadata stored in association therewith identifying whether the data block specifies a capability or a data value. At least one type of capability is a bounded pointer. Responsive to a write to a data block in the cache storage a capability metadata modification marker is set in association with the data block, indicative of whether the capability metadata associated with the data block has changed since the data block was stored in the cache storage. This supports the security of the system, such that modification of the use of a data block from a data value to a capability cannot take place unless intended. Efficiencies may also result when capability metadata is stored separately from other data in memory, as fewer accesses to memory can be made.

公开(公告)号：US11048617B2

公开(公告)日：2021-06-29

申请号：US16971415

申请日：2019-01-17

Applicant: Arm Limited

Inventor： Michael John Williams ,  Graeme Peter Barnes ,  John Michael Horley

IPC: G06F11/36

Abstract: A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items. The number of metadata items accessed by each instance of the metadata access operation is non-deterministic by the debugger from the metadata access operation. However, the at least one command is such that the plurality of instances of the metadata access operation are performed by the processing circuitry without the debugger interrogating the processing circuitry between each instance of the metadata access operation to determine progress in the number of metadata items accessed. Such an approach can significantly improve the efficiency of performing such accesses to metadata items under debugger control.

公开(公告)号：US11461128B2

公开(公告)日：2022-10-04

申请号：US16606400

申请日：2018-04-19

Applicant: ARM LIMITED

Inventor： Graeme Peter Barnes

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/48

Abstract: An apparatus and method are provided for managing use of capabilities. The apparatus has processing circuitry to execute instructions, and a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain operations performed by the processing circuitry when executing instructions. The processing circuitry is operable at a plurality of exception levels, each exception level having different software execution privilege. Further, capability configuration storage is provided to identify capability configuration information for each of the plurality of exception levels. For each exception level, the capability configuration information identifies at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by capabilities. During a switch operation from a source exception level to a target exception level, the capability configuration information in the capability configuration storage pertaining to at least one of the source exception level and the destination exception level is used to determine how execution state of the processing circuitry is managed during the switch operation. This provides a great deal of flexibility in the management of capabilities.

公开(公告)号：US11327903B2

公开(公告)日：2022-05-10

申请号：US16647729

申请日：2018-12-10

Applicant: ARM LIMITED

Inventor： Graeme Peter Barnes

IPC: G06F12/00 ,  G06F12/14 ,  G06F9/30

Abstract: An apparatus has memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. An instruction decoder decodes a multiple guard tag setting instruction to control the memory access circuitry to trigger memory accesses to update the guard tags associated with at least two consecutive blocks of one or more memory locations.

公开(公告)号：US11138128B2

公开(公告)日：2021-10-05

申请号：US16647661

申请日：2019-01-25

Applicant: ARM LIMITED

Inventor： Graeme Peter Barnes

IPC: G06F12/1009

Abstract: An apparatus comprises address translation circuitry to perform a translation of virtual addresses into physical addresses in dependence on stored page table mappings between the virtual addresses and the physical addresses. The stored page table mappings comprise tag-guard control information. The apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target physical address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target physical address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target physical address. The memory access circuitry is arranged to perform a non-tag-guarded memory access to the addressed location in response to the target physical address without performing the guard-tag check in dependence on the tag-guard control information.

公开(公告)号：US11030121B2

公开(公告)日：2021-06-08

申请号：US16055240

申请日：2018-08-06

Applicant: Arm Limited

Inventor： Daniel Arulraj ,  Lee Evan Eisen ,  Graeme Peter Barnes

IPC: G06F12/00 ,  G06F12/14 ,  G06F9/30 ,  G06F12/02 ,  G06F9/35 ,  G06F12/04 ,  G06F12/06 ,  G06F9/34

Abstract: An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant p−q−e bits of the lower limit and the upper limit is derivable from the most significant p−q−e bits of the pointer value. Mapping circuitry is used to map the lower limit mantissas and upper limit mantissas of the first and second bounded pointer representations to a q+x bit address space comprising 2x regions of size 2n1, where n1 is the value of n determined when using the exponent value of the first bounded pointer representation. Mantissa extension circuitry extends the lower limit and upper limit mantissas for each bounded pointer representation to create extended lower limit and upper limit mantissas comprising q+x bits, where a most significant x bits of each extended limit mantissa are mapping bits identifying which region the associated limit mantissa is mapped to. The determination circuitry then determines whether the region for the second pointer is a subset of the region for the first bounded pointer by comparing the extended lower and upper limit mantissas.