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公开(公告)号：US11429532B2
公开(公告)日：2022-08-30
申请号：US15501278
申请日：2015-06-23
Applicant: ARM Limited
Inventor： Ali Ghassan Saidi , Richard Roy Grisenthwaite
IPC: G06F12/08 , G06F12/10 , G06F12/12 , G06F12/0891 , G06F12/0815 , G06F12/0804 , G06F12/0875 , G06F12/1009 , G06F12/126 , G06F9/30 , G06F9/46
Abstract: An apparatus for processing data and a method of data processing are provided. A processor core in the apparatus performs data processing operations in response to a sequence of instructions, including write operations which write data items to a non-volatile memory. A write-back cache stores local copies of the data items retrieved from the memory and written to the memory by the processor core. A storage unit is provided which stores indications of the write operations initiated by the processor core and the processor core is configured to respond to an end instruction by causing the local copies of data items which are the subject of the write operations by the processor core, and for which an indication is stored in the storage unit, to be cleaned from the write-back cache to the memory. The indications of the write operations stored in the storage unit are then cleared.
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公开(公告)号：US10558590B2
公开(公告)日：2020-02-11
申请号：US15574938
申请日：2016-04-26
Applicant: ARM LIMITED
Abstract: A data processing system for processing data using a memory having a plurality of memory regions, a given memory region within said plurality of memory regions having an associated owning process having exclusive rights to control access to said given memory region, said system comprising: a security controller to: receive a request to initialise a guest execution environment; claim one or more regions of memory to be owned by said security controller; store executable program code of said guest execution environment within said one or more regions of memory; and transfer ownership of said one or more regions to said guest execution environment.
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公开(公告)号：US10394557B2
公开(公告)日：2019-08-27
申请号：US15538365
申请日：2015-11-23
Applicant: ARM LIMITED
Inventor： Stephan Diestelhorst , Michael John Williams , Richard Roy Grisenthwaite , Matthew James Horsnell
Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.
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公开(公告)号：US10169573B2
公开(公告)日：2019-01-01
申请号：US15284830
申请日：2016-10-04
Applicant: ARM Limited
Inventor： Thomas Christopher Grocutt , Richard Roy Grisenthwaite
Abstract: A data processing apparatus including circuitry for performing data processing, a plurality of registers; and a data store including regions having different secure levels, at least one secure region (for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in a less secure domain) and a less secure region (for storing less secure data). The circuitry is configured to determine which stack to store data to, or load data from, in response to the storage location of the program code being executed. In response to program code calling a function to be executed, the function code being stored in a second region, the second region having a different secure level to the first region, the data processing circuitry is configured to determine which of the first and second region have a lower secure level.
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公开(公告)号：US10025923B2
公开(公告)日：2018-07-17
申请号：US14935504
申请日：2015-11-09
Applicant: ARM Limited
Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.
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Patent Agency Ranking
公开(公告)号：US09619225B2
公开(公告)日：2017-04-11
申请号：US14878188
申请日：2015-10-08
Applicant: ARM Limited
Inventor： David James Seal , Richard Roy Grisenthwaite , Nigel John Stephens
CPC classification number: G06F9/3016 , G06F7/764 , G06F7/768 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element. Bitwise logical instructions are also described.
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公开(公告)号：US09330035B2
公开(公告)日：2016-05-03
申请号：US13900777
申请日：2013-05-23
Applicant: ARM LIMITED
Inventor： Anthony Jebson , Richard Roy Grisenthwaite , Michael Alexander Kennedy , Ian Michael Caulfield
CPC classification number: G06F13/24 , G06F9/4812 , G06F9/4818
Abstract: A data processing device comprises a plurality of system registers and a set of interrupt handling registers for controlling handling of an incoming interrupt. The device also includes processing circuitry configured to execute software of the plurality of execution levels, and interrupt controller circuitry configured to route said incoming interrupts to interrupt handling software that is configured to run at one of said plurality of execution levels, and register access control circuitry configured to dynamically control access to at least some of said interrupt handling registers in dependence upon one of said plurality of execution levels that said incoming interrupt is routed to. The interrupt handling software configured to run at a particular execution level does not have access to interrupt handling registers for handling a different incoming interrupt that is routed to interrupt handling software that is configured to run at a more privileged execution level.
Abstract translation: 数据处理装置包括多个系统寄存器和一组用于控制进入中断的处理的中断处理寄存器。 所述设备还包括被配置为执行所述多个执行级别的软件的处理电路，以及被配置为将所述输入中断路由到中断处理软件的中断控制器电路，所述中断处理软件被配置为在所述多个执行级中的一个执行级别运行，并且将访问控制电路 配置为根据所述多个执行级别中的一个来动态地控制对至少一些所述中断处理寄存器的访问，所述多个执行级别中的所述进入中断被路由到。 配置为在特定执行级别运行的中断处理软件无法访问中断处理寄存器，用于处理被配置为以更特权的执行级运行的中断处理软件的不同输入中断。
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公开(公告)号：US08966282B2
公开(公告)日：2015-02-24
申请号：US13627209
申请日：2012-09-26
Applicant: ARM Limited
CPC classification number: G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/12 , H04L2209/125
Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
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公开(公告)号：US20250021487A1
公开(公告)日：2025-01-16
申请号：US18711242
申请日：2022-04-28
Applicant: Arm Limited
Inventor： Richard Roy Grisenthwaite
IPC: G06F12/1009
Abstract: Memory management circuitry (28) supports two-stage address translation based on a stage-1 and stage-2 translation table structures. Stage-2 access permission information specified by a stage-2 translation table entry has an encoding specifying whether a corresponding memory region has a partially-read-only permission indicating that write requests to the memory region corresponding to the target intermediate address, issued when processing circuitry (4) is in a predetermined execution state, are permitted for a restricted subset of write request types (including metadata-updating write requests for updating access tracking metadata in translation table entries) but prohibited for other write request types. The memory management circuitry (28) rejects a memory access request when the stage-2 access permission information of a corresponding stage-2 translation table entry specifies the partially-read-only permission and the memory access request is a write request, other than the restricted subset of write request types, issued in the predetermined execution state.
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公开(公告)号：US11989134B2
公开(公告)日：2024-05-21
申请号：US17907178
申请日：2021-03-08
Applicant: ARM LIMITED
Inventor： Yuval Elad , Jason Parker , Richard Roy Grisenthwaite , Simon John Craske , Alexander Donald Charles Chadwick
CPC classification number: G06F12/10 , G06F3/0622 , G06F3/0637 , G06F3/0673
Abstract: An apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.
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