公开(公告)号：US09146870B2

公开(公告)日：2015-09-29

申请号：US13949434

申请日：2013-07-24

Applicant: ARM LIMITED

Inventor： Hedley James Francis ,  Robert Martin Elliott ,  Ian Victor Devereux ,  Daren Croxford

IPC: G06F13/38 ,  G06F12/08 ,  G06F12/12 ,  G06F9/52 ,  G06F3/03

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value. The processor is configured in response to the predefined request to perform the operation on data within the storage location allocated to the data item.

Abstract translation: 一种处理装置，包括：用于处理数据的几个处理器; 包括对所有处理器可访问的存储器以及对应于每个处理器的多个高速缓存的分级存储器系统，每个高速缓存可由对应的处理器访问，并且包括存储位置和对应的指示符。 还存在用于维持分层存储器系统中存储的数据的一致性的高速缓存一致性控制电路。 处理器被配置为响应于接收到对数据项执行操作的预定义请求，以确定与接收到请求的处理器相对应的高速缓存是否具有分配给数据项的存储位置。 如果不是，则处理装置被配置为：将缓存内的存储位置分配给数据项，设置与存储位置相对应的指示符，以指示存储位置正在存储增量值，将分配的存储位置中的数据设置为 一个初始值。 处理器被配置为响应于对分配给数据项的存储位置内的数据执行操作的预定义请求。

公开(公告)号：US20150032970A1

公开(公告)日：2015-01-29

申请号：US13949434

申请日：2013-07-24

Applicant: Arm Limited

Inventor： Hedley James Francis ,  Robert Martin Elliott ,  Ian Victor Devereux ,  Daren Croxford

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value. The processor is configured in response to the predefined request to perform the operation on data within the storage location allocated to the data item.

Abstract translation: 一种处理装置，包括：用于处理数据的几个处理器; 包括对所有处理器可访问的存储器以及对应于每个处理器的多个高速缓存的分级存储器系统，每个高速缓存可由对应的处理器访问，并且包括存储位置和对应的指示符。 还存在用于维持分层存储器系统中存储的数据的一致性的高速缓存一致性控制电路。 处理器被配置为响应于接收到对数据项执行操作的预定义请求，以确定与接收到请求的处理器相对应的高速缓存是否具有分配给数据项的存储位置。 如果不是，则处理装置被配置为：将缓存内的存储位置分配给数据项，设置与存储位置相对应的指示符，以指示存储位置正在存储增量值，将分配的存储位置中的数据设置为 一个初始值。 处理器被配置为响应于对分配给数据项的存储位置内的数据执行操作的预定义请求。