公开(公告)号：US20220129186A1

公开(公告)日：2022-04-28

申请号：US17078304

申请日：2020-10-23

Applicant: Arm Limited

Inventor： Ho-Seop KIM ,  Joseph Michael PUSDESRIS ,  Miles Robert DOOLEY

IPC: G06F3/06

Abstract: A request node is provided, that includes request circuitry for issuing outgoing memory access requests to a remote node. Status receiving circuitry receives statuses regarding remote memory access requests at the remote node and control circuitry controls at least one of a rate or an aggression at which the outgoing memory access requests are issued to the remote node in dependence on at least some of the statuses. The control circuitry is inhibited from controlling the rate or the aggression until multiple statuses are received.

公开(公告)号：US20230418766A1

公开(公告)日：2023-12-28

申请号：US18253621

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Klas Magnus BRUCE ,  Jamshed JALAL ,  Dimitrios KASERIDIS ,  Gurunath RAMAGIRI ,  Ho-Seop KIM ,  Andrew John TURNER ,  Rania Hussein Hassan MAMEESH

IPC: G06F12/126 ,  G06F12/0811

CPC classification number: G06F12/126 ,  G06F12/0811

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.