公开(公告)号：US20210149833A1

公开(公告)日：2021-05-20

申请号：US16685082

申请日：2019-11-15

Applicant: Arm Limited

Inventor： Tushar P. RINGE ,  Jamshed JALAL ,  Gurunath RAMAGIRI ,  Ashok Kumar TUMMALA ,  Mark David WERKHEISER

IPC: G06F13/40 ,  G06F9/46

Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order. The requester element is then responsive to the ordered channel indication to control timing of issuance from the requester element of at least one signal relating to one or more transactions after the given transaction in the sequence. By such an approach, the ordering flow adopted for ordered transactions can be varied by the requester element in dependence on the presence or absence of an ordered channel, whilst enabling interconnect-agnostic requester element designs to be utilised.

公开(公告)号：US20200089634A1

公开(公告)日：2020-03-19

申请号：US16135149

申请日：2018-09-19

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Tushar P. RINGE ,  Anitha KONA ,  Andrew Brookfield SWAINE ,  Michael Andrew CAMPBELL

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/364

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device. The slave device has transfer identifier generation circuitry for generating, for each data transfer, a transfer identifier to be transmitted over the connection medium to identify which data item in the plurality of data items is being transferred by that data transfer. The master device has buffer circuitry to buffer data items received by the plurality of data transfers, and to employ the transfer identifier provided for each data transfer to cause the plurality of data items to be provided to the processing circuitry in a determined order irrespective of an order in which the data items are transferred to the master device via the plurality of data transfers. This can significantly reduce the overhead required to manage the supply of the data items to the processing circuitry in the required determined order.

公开(公告)号：US20200042463A1

公开(公告)日：2020-02-06

申请号：US16053899

申请日：2018-08-03

Applicant: Arm Limited

Inventor： Tessil THOMAS ,  Jamshed JALAL ,  Andrea PELLEGRINI ,  Anitha KONA

IPC: G06F12/14 ,  G06F13/42 ,  G06F12/1081

Abstract: An apparatus includes a first device configured to generate a transaction request targeted to a first address, a switch, coupled to the first device and configured to the route the transaction request, a port coupled to the peripheral switch and the data processing network, and a system memory management unit, coupled to the port. The system memory management unit is configured for receiving an address query for the first address from the peripheral port translating the first address to a second address, accessing attributes of a device associated with the second address and responding to the query. Access validation for the transaction request is confirmed or denied dependent upon the second address and the attributes of the device associated with the second address. The first device may be a peripheral device, the switch may be a peripheral switch and the port may be a peripheral port.

公开(公告)号：US20190342034A1

公开(公告)日：2019-11-07

申请号：US16027864

申请日：2018-07-05

Applicant: Arm Limited

Inventor： Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL ,  Tushar P. RINGE

IPC: H04L1/16 ,  H04L29/08

Abstract: In a data processing network comprising one or more Request Nodes and a Home Node coupled via a coherent interconnect, a Request Node requests data from the Home Node. The requested data is sent, via the interconnect, to the Request Node in a plurality of data beats, where a first data beat of the plurality of data beats is received at a first time and a last data beat is received at a second time. Responsive to receiving the first data beat, the Request Node sends an acknowledgement message to the Home Node. Upon receipt of the acknowledgement message, the Home Node frees resources allocated to the read transaction. In addition, the Home Node is configured to allow snoop requests for the data to the Request Node to be sent to the Request Node before all beats of the requested data have been received by the Request Node.

公开(公告)号：US20180225216A1

公开(公告)日：2018-08-09

申请号：US15427421

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael FILIPPO ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Alex James WAUGH ,  Geoffray LACOURBA ,  Paul Gilbert MEYER ,  Bruce James MATHEWSON ,  Phanindra Kumar MANNAVA

IPC: G06F12/0862 ,  G06F15/78

CPC classification number: G06F12/0862 ,  G06F11/34 ,  G06F12/0811 ,  G06F12/0833 ,  G06F15/7825 ,  G06F2212/502 ,  G06F2212/507

Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

公开(公告)号：US20180225214A1

公开(公告)日：2018-08-09

申请号：US15427459

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Michael FILIPPO ,  Paul Gilbert MEYER ,  Alex James WAUGH ,  Geoffray Matthieu LACOURBA

IPC: G06F12/0831 ,  G06F9/46

CPC classification number: G06F12/0835 ,  G06F12/0808 ,  G06F2212/1024 ,  G06F2212/621

Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.

公开(公告)号：US20180217932A1

公开(公告)日：2018-08-02

申请号：US15422691

申请日：2017-02-02

Applicant: ARM Limited

Inventor： Tushar P. RINGE ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Phanindra Kumar MANNAVA

IPC: G06F12/0831 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/063 ,  G06F12/0868 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/387 ,  G06F13/4256 ,  G06F13/4273 ,  G06F13/4291 ,  G06F15/7807 ,  G06F2212/621

Abstract: A home node of a data processing apparatus that includes a number of devices coupled via an interconnect system is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and the data bus width of the interconnect system. Data is transferred as a cache line serialized into a number of data beats. The home node may be configured to minimize the number of data transfers on the third data bus or to minimize latency in the transfer of the critical beat of the cache line.

公开(公告)号：US20240061613A1

公开(公告)日：2024-02-22

申请号：US17890456

申请日：2022-08-18

Applicant: Arm Limited

Inventor： Pavel SHAMIS ,  Honnappa NAGARAHALLI ,  Jamshed JALAL

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0635 ,  G06F3/0673 ,  G06F3/0604

Abstract: There is provided an apparatus, method, and computer-readable medium. The apparatus comprises interconnect circuitry to couple a device to one or more processing elements and to one or more storage structures. The apparatus also comprises stashing circuitry configured to receive stashing transactions from the device, each stashing transaction comprising payload data and control data. The stashing circuitry is responsive to a given stashing transaction whose control data identifies a plurality of portions of the payload data, to perform a plurality of independent stashing decision operations, each of the plurality of independent stashing decision operations corresponding to a respective portion of the plurality of portions of payload data and comprising determining, with reference to the control data, whether to direct the respective portion to one of the one or more storage structures or whether to forward the respective portion to memory.

公开(公告)号：US20230221866A1

公开(公告)日：2023-07-13

申请号：US18000761

申请日：2021-05-20

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Gurunath RAMAGIRI ,  Tushar P RINGE ,  Mark David WERKHEISER ,  Ashok Kumar TUMMALA ,  Dimitrios KASERIDIS

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0653

Abstract: A technique for handling memory access requests is described. An apparatus has an interconnect for coupling a plurality of requester elements with a plurality of slave elements. The requester elements are arranged to issue memory access requests for processing by the slave elements. An intermediate element within the interconnect acts as a point of serialisation to order the memory access requests issued by requester elements via the intermediate element. The intermediate element has tracking circuitry for tracking handling of the memory access requests accepted by the intermediate element. Further, request acceptance management circuitry is provided to identify a target slave element amongst the plurality of slave elements for that given memory access request, and to determine whether the given memory access request is to be accepted by the intermediate element dependent on an indication of bandwidth capability for the target slave element.

公开(公告)号：US20210103525A1

公开(公告)日：2021-04-08

申请号：US16591827

申请日：2019-10-03

Applicant: Arm Limited

Inventor： Phanindra Kumar MANNAVA ,  Bruce James MATHEWSON ,  Jamshed JALAL

IPC: G06F12/0897 ,  G06F12/0871 ,  G06F12/0868

Abstract: An apparatus and method are provided for handling cache maintenance operations. The apparatus has a plurality of requester elements for issuing requests and at least one completer element for processing such requests. A cache hierarchy is provided having a plurality of levels of cache to store cached copies of data associated with addresses in memory. A requester element may be arranged to issue a cache maintenance operation request specifying a memory address range in order to cause a block of data associated with the specified memory address range to be pushed through at least one level of the cache hierarchy to a determined visibility point in order to make that block of data visible to one or more other requester elements. The given requester element may be arranged to detect when there is a need to issue a write request prior to the cache maintenance operation request in order to cause a write operation to be performed in respect of data within the specified memory address range, and in that event to generate a combined write and cache maintenance operation request to be issued instead of the write request and a subsequent cache maintenance operation request. A recipient completer element that receives the combined write and cache maintenance operation request may then be arranged to initiate processing of the cache maintenance operation required by the combined write and cache maintenance operation request without waiting for the write operation to complete. This can significantly reduce latency in the handling of cache maintenance operations, and can provide for reduced bandwidth utilisation.