公开(公告)号：US11016774B1

公开(公告)日：2021-05-25

申请号：US16695917

申请日：2019-11-26

Applicant: Arm Limited

Inventor： Luka Dejanovic ,  William Robert Stoye

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/38 ,  G06T1/60 ,  G06F9/30

Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.

公开(公告)号：US20210157600A1

公开(公告)日：2021-05-27

申请号：US16695917

申请日：2019-11-26

Applicant: Arm Limited

Inventor： Luka Dejanovic ,  William Robert Stoye

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/60

Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.

公开(公告)号：US20200233726A1

公开(公告)日：2020-07-23

申请号：US16254286

申请日：2019-01-22

Applicant: Arm Limited

Inventor： Luka Dejanovic ,  Mladen Wilder

IPC: G06F9/52 ,  G06F9/48

Abstract: A data processing system including a data processor which is operable to execute programs to perform data processing operations and in which execution threads executing a program to perform data processing operations may be grouped together into thread groups. The data processor comprises a cross-lane permutation circuit which is operable to perform processing for cross-lane instructions which require data to be permuted (copied or moved) between the threads of a thread group. The cross-lane permutation circuit has plural data lanes between which data may be permuted (moved or copied). The number data lanes is fewer than the number of threads in a thread group.