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公开(公告)号：US20200233726A1
公开(公告)日：2020-07-23
申请号：US16254286
申请日：2019-01-22
Applicant: Arm Limited
Inventor： Luka Dejanovic , Mladen Wilder
Abstract: A data processing system including a data processor which is operable to execute programs to perform data processing operations and in which execution threads executing a program to perform data processing operations may be grouped together into thread groups. The data processor comprises a cross-lane permutation circuit which is operable to perform processing for cross-lane instructions which require data to be permuted (copied or moved) between the threads of a thread group. The cross-lane permutation circuit has plural data lanes between which data may be permuted (moved or copied). The number data lanes is fewer than the number of threads in a thread group.
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公开(公告)号：US10726606B2
公开(公告)日：2020-07-28
申请号：US16279882
申请日：2019-02-19
Applicant: Arm Limited
Inventor： Peter William Harris , Mladen Wilder
Abstract: When a shader program is to be executed by a graphics processor, the graphics processor is caused to execute at least two variants of the shader program and the operation of the graphics processor when executing execution threads for the different variants of the shader program is monitored.A variant of the shader program to be executed by subsequent execution threads that are to execute the shader program is then selected based on the monitoring of the operation of the shading stage when executing the execution threads for the different variants of the shader program.
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公开(公告)号：US09304926B2
公开(公告)日：2016-04-05
申请号：US13948658
申请日：2013-07-23
Applicant: ARM LIMITED
Inventor： Ian Bratt , Mladen Wilder , Ole Henrik Jahren
IPC: G06F12/08
CPC classification number: G06F12/0855 , G06F12/0815 , G06F12/0828 , G06F12/0831 , Y02D10/13
Abstract: A coherent memory system includes a plurality of level 1 cache memories 6 connected via interconnect circuitry 18 to a level 2 cache memory 8. Coherency control circuitry 10 manages coherency between lines of data. Evict messages from the level 1 cache memories to the coherency control circuitry 10 are sent via the read address channel AR. Read messages are also sent via the read address channel AR. The read address channel AR is configured such that a read message may not be reordered relative to an evict message. The coherency control circuitry 10 is configured such that a read message will not be processed ahead of an evict message. The level 1 cache memories 6 do not track in-flight evict messages. No acknowledgement of an evict message is sent from the coherency control circuitry 10 back to the level 1 cache memory 6.
Abstract translation: 相干存储器系统包括经由互连电路18连接到级别2高速缓冲存储器8的多个1级高速缓冲存储器6。一致性控制电路10管理数据线之间的相干性。 通过读地址信道AR发送从1级缓存存储器到相干性控制电路10的消息。 读消息也通过读地址通道AR发送。 读地址信道AR被配置为使得读消息可能不相对于逐出消息重新排序。 一致性控制电路10被配置为使得读取消息将不会在逐出消息之前被处理。 级别1缓存存储器6不跟踪飞行中的逐出消息。 从相关性控制电路10不发送逐出消息的确认回到1级缓存存储器6。
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公开(公告)号：US20190259193A1
公开(公告)日：2019-08-22
申请号：US16279882
申请日：2019-02-19
Applicant: Arm Limited
Inventor： Peter William Harris , Mladen Wilder
Abstract: When a shader program is to be executed by a graphics processor, the graphics processor is caused to execute at least two variants of the shader program and the operation of the graphics processor when executing execution threads for the different variants of the shader program is monitored.A variant of the shader program to be executed by subsequent execution threads that are to execute the shader program is then selected based on the monitoring of the operation of the shading stage when executing the execution threads for the different variants of the shader program.
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