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公开(公告)号：US11977884B2
公开(公告)日：2024-05-07
申请号：US16468108
申请日：2017-11-10
Applicant: ARM LIMITED
Inventor： Jacob Eapen , Grigorios Magklis , Mbou Eyole
CPC classification number: G06F9/30032 , G06F9/30018 , G06F9/30036 , G06F9/30109
Abstract: A replicate elements instruction defining a plurality of variable length segments in a result vector controls processing circuitry (80) to generate a result vector in which, in each respective segment, a repeating value is repeated throughout that segment of the result vector, the repeating value comprising a data value or element index of a selected data element of a source vector. This instructions is useful for accelerating processing of data structures smaller than the vector length.
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公开(公告)号：US11775297B2
公开(公告)日：2023-10-03
申请号：US16651045
申请日：2018-08-21
Applicant: Arm Limited
Inventor： Grigorios Magklis , Matthew James Horsnell , Stephan Diestelhorst
CPC classification number: G06F9/30021 , G06F9/30058 , G06F9/30076 , G06F9/30094 , G06F9/3842 , G06F9/467
Abstract: In a system providing transactional memory support, a transaction nesting depth testing instruction is provided for triggering processing circuitry 4 to set at least one status value to one of a plurality of states depending on a transaction nesting depth indicative of a number of executed transaction start instructions of a given thread for which the corresponding transaction remains unaborted and uncommitted, the plurality of states including a first state selected when the transaction nesting depth is 1 and at least one further state selected when the transaction nesting depth is greater than or less than 1. The supported ISA enables the setting of the at least one status value and a conditional branch conditional on the at least one status value being in the first state to be performed in response to a single transaction nesting depth testing instruction and a single conditional branch instruction.
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公开(公告)号：US11327752B2
公开(公告)日：2022-05-10
申请号：US16487256
申请日：2018-02-02
Applicant: ARM LIMITED
Inventor： Grigorios Magklis , Nigel John Stephens , Jacob Eapen , Mbou Eyole , David Hennah Mansell
Abstract: A data processing apparatus, a method of operating a data processing apparatus, a non-transitory computer readable storage medium, and an instruction are provided. The instruction specifies a first source register, a second source register, and an index. In response to the instruction control signals are generated, causing processing circuitry to perform a data processing operation with respect to each data group in the first source register and the second source register to generate respective result data groups forming a result of the data processing operation. Each of the first source register and the second source register has a size which is an integer multiple at least twice a predefined size of the data group, and each data group comprises a plurality of data elements. The operands of the data processing operation for each data group are a selected data element identified in the data group of the first source register by the index and each data element in the data group of the second source register. A technique for element-by-vector operation which is readily scalable as the register width grows.
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公开(公告)号：US11947962B2
公开(公告)日：2024-04-02
申请号：US16468098
申请日：2017-11-10
Applicant: ARM LIMITED
Inventor： Jacob Eapen , Grigorios Magklis , Mbou Eyole
CPC classification number: G06F9/30032 , G06F9/30018 , G06F9/30036 , G06F9/30109
Abstract: In response to a replicate partition instruction specifying partition information defining positions of a plurality of variable size partitions within a result vector, an instruction decoder (20) controls the processing circuitry (80) to generate a result vector in which each partition having more than one data element comprises data values or element indices of a sequence of data elements of a source vector starting or ending at a selected data element position. This instruction can be useful for accelerating processing of data structures smaller than the vector length.
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公开(公告)号：US11663034B2
公开(公告)日：2023-05-30
申请号：US16651017
申请日：2018-08-21
Applicant: Arm Limited
Inventor： Matthew James Horsnell , Grigorios Magklis , Richard Roy Grisenthwaite , Stephan Diestelhorst
CPC classification number: G06F9/467 , G06F9/3009 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F9/466 , G06F9/4812 , G06F11/1402 , G06F11/1474
Abstract: A data processing apparatus has processing circuitry with transactional memory support circuitry to support execution of a transaction using transactional memory. In response to an exception mask updating instruction which updates exception mask information to enable at least one subset of exceptions which was disabled at the start of processing of a transaction, the processing circuitry permits un-aborted processing of one or more subsequent instruction of the transaction that follow the exception mask update instruction.
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Patent Agency Ranking
公开(公告)号：US11422808B2
公开(公告)日：2022-08-23
申请号：US17258287
申请日：2019-05-09
Applicant: Arm Limited
Inventor： Matthew James Horsnell , Grigorios Magklis , Stephan Diestelhorst
Abstract: An apparatus comprising: processing circuitry to process threads of data processing; and transactional memory support circuitry to support execution of a transaction within a thread processed by the processing circuitry. In response to a transactional compare-and-discard instruction executed within a given transaction, specifying a target address and a compare value, the processing circuitry loads a target data value from a memory location corresponding to the target address; sets at least one condition status indication depending on a result of comparing the target data value and the compare value; and discards the target data value without adding the target address to a working set of addresses tracked for the given transaction. This is useful for enabling thread level speculation to be implemented on a transactional memory architecture.
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公开(公告)号：US11615032B2
公开(公告)日：2023-03-28
申请号：US16625102
申请日：2018-06-01
Applicant: ARM LIMITED
Inventor： Matthew James Horsnell , Grigorios Magklis , Richard Roy Grisenthwaite
IPC: G06F3/06 , G06F12/1027 , G06F9/46 , G06F9/54 , G06F12/0873
Abstract: A data processing system (2) including one or more transaction buffers (16, 18, 20) storing address translation data executes translation buffer invalidation instructions TLBI within respective address translation contexts VMID, ASID, X. Translation buffer invalidation signals generated as a consequence of execution of the translation buffer invalidation instructions are broadcast to respective translation buffers and include signals which specify the address translation context of the translation buffer invalidation instruction that was executed. This address translation context specified within the translation buffer invalidation signals is used to gate whether or not those translation buffer invalidation signals when received by translation buffers which are potential targets for the invalidation are or are not flushed. The address translation context data provided within the translation buffer invalidation signals may also be used to control whether or not local memory transactions for a local transactional memory access are or are not aborted upon receipt of the translation buffer invalidation signals.
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8.发明授权公开(公告)号：US11579873B2
公开(公告)日：2023-02-14
申请号：US17255001
申请日：2019-05-09
Applicant: Arm Limited
Inventor： Matthew James Horsnell , Grigorios Magklis , Richard Roy Grisenthwaite , Nathan Yong Seng Chong
Abstract: An apparatus is described with support for transactional memory and load/store-exclusive instructions using an exclusive monitor indication to track exclusive access to a given address. In response to a predetermined type of load instruction specifying a load target address, which is executed within a given transaction, any exclusive monitor indication previously set for the load target address is cleared. In response to a load-exclusive instruction, an abort is triggered for a transaction for which the given address is specified as one of its working set of addresses. This helps to maintain mutual exclusion between transactional and non-transactional threads even if there is load speculation in the non-transactional thread.
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公开(公告)号：US11513796B2
公开(公告)日：2022-11-29
申请号：US16487258
申请日：2018-01-26
Applicant: ARM LIMITED
Inventor： David Hennah Mansell , Grigorios Magklis
Abstract: A data processing apparatus, a method of operating a data processing apparatus, a non-transitory computer readable storage medium, and an instruction are provided. The instruction specifies a first source register, a second source register, and a set of N accumulation registers. In response to the instruction control signals are generated, causing processing circuitry to extract N data elements from content of the first source register, perform a multiplication of each of the N data elements by content of the second source register, and apply a result of each multiplication to content of a respective target register of the set of N accumulation registers. As a result plural (N) multiplications are performed in a manner that effectively provides a multiplier N times the register width, but without requiring the register file to be made N times larger.
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公开(公告)号：US11314514B2
公开(公告)日：2022-04-26
申请号：US15741303
申请日：2016-06-23
Applicant: ARM Limited
Inventor： Nigel John Stephens , Grigorios Magklis , Alejandro Martinez Vicente , Nathanael Premillieu
Abstract: A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.
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