公开(公告)号：US11269634B2

公开(公告)日：2022-03-08

申请号：US16531206

申请日：2019-08-05

Applicant: Arm Limited

Inventor： David Hennah Mansell ,  Nigel John Stephens ,  Matthew Lucien Evans

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38

Abstract: A data processing apparatus is provided comprising: a plurality of storage circuits to store data. Execution circuitry performs one or more operations using the storage circuits in response to instructions. The instructions include a relinquish instruction. The execution circuitry responds to the relinquish instruction by indicating that at least one of the plurality of storage circuits is an unused storage circuit and the execution circuitry affects execution of future instructions based on the unused storage circuit after executing the relinquish instruction.

公开(公告)号：US10366741B2

公开(公告)日：2019-07-30

申请号：US15711116

申请日：2017-09-21

Applicant: ARM LIMITED

Inventor： Neil Burgess ,  Nigel John Stephens ,  Lee Evan Eisen ,  Jaime Ferragut Martinez-Vara De Rey

IPC: G11C11/56 ,  G11C11/4094

Abstract: Circuitry comprises: a set of bit processing circuitries to apply two or more successive instances of bitwise processing to an ordered bit array; each bit processing circuitry for a given bit position within the ordered bit array comprising: bit shifting circuitry to selectively apply a bit shift of a respective input bit to a next bit processing circuitry in a first direction relative to the ordered bit array, in response to an active state of a bit shift control signal, the bit shifting circuitry not applying the bit shift in response to an inactive state of the bit shift control signal; and bit shift control circuitry to selectively allow or inhibit a bit shifting operation in response to one or more inhibit control signals; in which: the bit shift control circuitry is configured to selectively propagate an output inhibit control signal, indicating that a bit shifting operation should be inhibited, as an inhibit control signal to bit processing circuitry applying a next instance of the bitwise processing at the given bit position, in dependence upon the bit shift control signal and the one or more inhibit control signals.

公开(公告)号：US12197916B2

公开(公告)日：2025-01-14

申请号：US18006813

申请日：2021-07-08

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  David Hennah Mansell ,  Richard Roy Grisenthwaite ,  Matthew Lucien Evans ,  Jelena Milanovic

IPC: G06F9/30 ,  G06F9/38

Abstract: Instruction decoder to decode processing instructions; one or more first registers; first processing circuitry to execute the decoded processing instructions in a first processing mode and configured to execute the decoded processing instructions using the one or more first registers; and control circuitry to execute the decoded processing instructions in a second processing mode using one or more second registers; the instruction decoder being configured to decode processing instructions selected from a first instruction set and a second instruction set in the second processing mode, in which one or both of the first and second instruction sets comprises at least one unique instruction set; the instruction decoder configured to decode one or more mode change instructions to change between the first and second processing mode; and the first processing circuitry configured to change the current processing mode between the first and second processing mode responding to executing mode change instruction.

公开(公告)号：US20240329996A1

公开(公告)日：2024-10-03

申请号：US18579804

申请日：2022-06-22

Applicant: Arm Limited

Inventor： Alejandro Martinez Vicente ,  Nigel John Stephens ,  Jelena Milanovic

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30036

Abstract: Apparatuses, methods and programs are disclosed relating to the predication of multiple vectors in vector processing. An encoding of predicate information is disclosed which comprises an element size and an element count, wherein the predicate information comprises a multiplicity of consecutive identical predication indicators given by the element count, each predication indicator corresponding to the element size.

公开(公告)号：US12061906B2

公开(公告)日：2024-08-13

申请号：US15745478

申请日：2016-06-15

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Jacob Eapen ,  Mbou Eyole

IPC: G06F9/315 ,  G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30018 ,  G06F9/30036

Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within sequential data element positions of the result vector starting from a first end of the result vector, and data elements from a second vector are output to the remaining result vector data element positions not occupied by the extracted data elements from the first vector.

公开(公告)号：US11354126B2

公开(公告)日：2022-06-07

申请号：US16975486

申请日：2019-02-15

Applicant: Arm Limited

Inventor： Michael John Williams ,  Nigel John Stephens

IPC: G06F9/30

Abstract: Data processing apparatus comprises vector processing circuitry to selectively apply vector processing operations defined by vector processing instructions to generate one or more data elements of a data vector comprising a plurality of data elements at respective data element positions of the data vector, according to the state of respective predicate flags associated with the positions of the data vector; and generator circuitry to generate instruction sample data indicative of processing activities of the vector processing circuitry for selected ones of the vector processing instructions, instruction sample data indicating at least the state of the predicate flags at execution of the selected vector processing instructions.

公开(公告)号：US10963245B2

公开(公告)日：2021-03-30

申请号：US16424718

申请日：2019-05-29

Applicant: Arm Limited

Inventor： David Raymond Lutz ,  Neil Burgess ,  Christopher Neal Hinds ,  Nigel John Stephens

IPC: G06F9/30 ,  H03M7/24

Abstract: An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.

公开(公告)号：US10795675B2

公开(公告)日：2020-10-06

申请号：US15761476

申请日：2016-09-14

Applicant: ARM LIMITED

Inventor： Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus 2 has instruction fusing circuitry 50 for fusing two or more instructions fetched from a data store to generate a fused instruction to be processed by processing circuitry 14. A move prefix instruction is provided which indicates to the instruction fusing circuitry 50 that the move prefix instruction can be fused with an immediately following data processing instruction without needing to compare registers specified by the move prefix instruction and the immediately following instruction. This enables the instruction fusing circuitry 50 to be implemented with reduced hardware and energy cost.

公开(公告)号：US10564968B2

公开(公告)日：2020-02-18

申请号：US15759914

申请日：2016-09-05

Applicant: ARM LIMITED

Inventor： Nigel John Stephens

IPC: G06F9/30 ,  G06F15/80

Abstract: First and second types of vector load instruction are provided. For the first type, a response action is performed when an exceptional condition is detected for a load operation performed for a first active data element of at least one vector register, but when the exceptional condition is detected for an active data element other than the first active data element, the response action is suppressed and element identifying information is stored identifying the element which caused the exceptional condition. For the second type, the response action is suppressed and the element identifying information is stored when the exceptional condition arises for any active data element. This approach is useful for allowing loop speculation and loop unrolling to be used together to improve performance of vectorised code.

公开(公告)号：US10521232B2

公开(公告)日：2019-12-31

申请号：US15431955

申请日：2017-02-14

Applicant: ARM Limited

Inventor： David James Seal ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC: G06F9/30 ,  G06F9/38 ,  G06F7/76

Abstract: A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.