公开(公告)号：US11204738B1

公开(公告)日：2021-12-21

申请号：US16891366

申请日：2020-06-03

Applicant: Arm Limited

Inventor： Nicholas Andrew Pfister

IPC: G06F7/08 ,  G06F5/01

Abstract: An apparatus and method are provided for performing bit permutation operations. The apparatus has an interface for receiving an input data operand and a control operand. The input data operand comprises one or more data elements, each data element comprising a plurality of bits, and the control operand provides control information identifying bit permutations required when performing a given bit permutation operation on each data element. The bit permute circuitry treats the input data operand as a plurality of fixed size data portions, each data element comprising one or more of the data portions with the number being dependent on the data element size. The bit permute circuitry performs bit permutation operations on each data portion of the input data operand, using the control information provided for that data portion, generating, for each data portion, at least one intermediate result. Result generation circuitry generates, from the intermediate results, a final result operand comprising one or more result elements, each result element providing the result of performing the given bit permutation operation on the corresponding data element of the input data operand. The result generation circuitry comprises a multi-level network of shifter circuits, shifter circuits at a first level performing shift operations using as inputs at least a subset of the intermediate results, and shifter circuits at each subsequent level performing shift operations using inputs derived from the outputs of the shifter circuits at a preceding level of the network. Control circuitry analyses the control information provided by the control operand in order to generate control signals that control the shift operations performed by the shifter circuits.

公开(公告)号：US10970070B2

公开(公告)日：2021-04-06

申请号：US16368930

申请日：2019-03-29

Applicant: Arm Limited

Inventor： Nicholas Andrew Pfister ,  Srinivas Vemuri ,  David Raymond Lutz

IPC: G06F9/30 ,  G06F7/483

Abstract: An apparatus has processing circuitry to perform, in response to decoding of an iterative-operation instruction by the instruction decoder, an iterative operation comprising at least two iterations of processing where one iteration depends on an operand generated in a previous iteration. Preliminary information generating circuitry performs a preliminary portion of processing for a given iteration to generate preliminary information. Result generating circuitry performs a remaining portion of processing for the given iteration, to generate a result value using the preliminary information. Forwarding circuitry forwards the result value as an operand for a next iteration of the iterative operation, for iterations other than the final iteration. The preliminary information generating circuitry starts performing the preliminary portion for the next iteration in parallel with the result generating circuitry completing the remaining portion for the current iteration, to improve performance.

公开(公告)号：US11327791B2

公开(公告)日：2022-05-10

申请号：US16546752

申请日：2019-08-21

Applicant: Arm Limited

Inventor： Michael David Achenbach ,  Robert Greg McDonald ,  Nicholas Andrew Pfister ,  Kelvin Domnic Goveas ,  Michael Filippo ,  . Abhishek Raja ,  Zachary Allen Kingsbury

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/52 ,  G06F9/50 ,  G06F9/30

Abstract: An apparatus provides an issue queue having a first section and a second section. Each entry in each section stores operation information identifying an operation to be performed. Allocation circuitry allocates each item of received operation information to an entry in the first section or the second section. Selection circuitry selects from the issue queue, during a given selection iteration, an operation from amongst the operations whose required source operands are available. Availability update circuitry updates source operand availability for each entry whose operation information identifies as a source operand a destination operand of the selected operation in the given selection iteration. A deferral mechanism inhibits from selection, during a next selection iteration, any operation associated with an entry in the second section whose source operands are now available due to that operation having as a source operand the destination operand of the selected operation in the given selection iteration.